Additional steps to those outlined:
emerge alsa-firmware
and... modprobe snd_hdsp
Changes also to cur to compile for GCC 4.1.1:
http://1010.co.uk/cur2-rme-feb2007.tar.gz
1] Added library for the older but more manageable FT232BL USB UART (USB to serial) component using online library component builder at:
http://www.rohrbacher.net/kicad/quicklib.php
library is at:
http://1010.co.uk/images/FT232BL.lib
packaging is TQFP32
2] Schematic is at:
http://1010.co.uk/images/atmega8usb.pdf
(note older PCB screenshot is incorrect)
3] 3 projected boards - independent UART and ATmega8 with circles for cpu_model, and both combined as above for 8 bit data interface sans parallel port
rough idea to edit video in Emacs Lisp:
http://www.gnu.org/software/emms/
;; emms-player-mplayer.el --- mplayer support for EMMS (defun emms-player-mplayer-seek (sec) "Depends on mplayer's -slave mode." (process-send-string emms-player-simple-process-name (format "pausing seek %d\n" sec)))
with subtitles and obviously using free software on GNU/Linux...
1] Using mencoder with subtitles specified a la:
/usr/bin/mencoder -of mpeg -mpegopts format=dvd -srate 48000 -ofps 25 -ovc lavc -oac lavc -lavcopts vcodec=mpeg2video:vrc_buf_size=1835:keyint=15:vrc_maxrate=9800:vbitrate=9800:acodec=ac3:aspect=4/3:abitrate=192 thefilm.avi -o test.mpeg2 -sub thesubtitles.srt -font ~/.mplayer/subfont.ttf -subfont-text-scale 3
breaks aspect with dvdauthor: unknown mpeg2 aspect ratio 1
results in DVD image with an incorrect aspect
note also the subfont.ttf as in previous attempts we couldn't scale the font
font can also be specified in ~/.mplayer/mencoder.conf:
font=~/.mplayer/subfont.ttf
Encoding to mpeg2 using ffmpeg works fine with dvdauthor and aspect but using spumux to add subtitles doesn't work - spumux 0.6.13 and darcs version result in drastic memory leaks.
2] Clumsy fix uses two passes:
mencoder thefilm.avi -ovc lavc -oac lavc -lavcopts aspect=4/3 -sub thesubtitles.srt -subfont-text-scale 3 -o outputfilm.avi ## then: ffmpeg -i outputfilm.avi -target pal-dvd -aspect 4:3 test.mpeg2 ## and then the usual processing with dvdauthor /usr/bin/dvdauthor -o ~/dvd -x ~/structure.xml mkisofs -dvd-video -o test.iso ~/dvd/ ##finally growisofs -dvd-compat -Z /dev/dvd=test.iso
for extra good measure dvdauthor's structure.xml:
<dvdauthor>
<vmgm>
<menus>
<video format="pal" aspect="4:3" />
</menus>
</vmgm>
<titleset>
<titles>
<pgc>
<vob file="~/test.mpeg2"/>
</pgc>
</titles>
</titleset>
</dvdauthor>
Computer controlled permutative switching of circuits (allows for 16 points to be connected) using 3 bits (serial data transmission) over USB or parallel port. Modular design of 2 serial/parallel boards (74HC595 shift register chips see: http://computerchristmas.com/index.phtml?link=how_to&:=25) and 4 switch boards (4016/4066 quad bilateral switches): http://www.doctronics.co.uk/4016.htm. Switching points are also exposed to CV (control voltage).
http://users.tkk.fi/~jwagner/electr/dc-rx/PCB_devel.htm
1] Straight print from PCBNEW menu under a range of options is unusable (tracks joined, offset and pads connected randomly).
2] Choose plot with Postscript option from file menu and write (in this case) xxxxx-Component.ps. Printing from this using gv is better but unusable also.
3] Run ps2pdf on this .ps and open resulting .pdf with xpdf. Print from this.
(further notes: print command for our CUPS shared printer is lpr -P printer, resolution was set by way of web interface to 600 dpi)
next stage exposure (UV light) and photoresist:
http://www.electricstuff.co.uk/pcbs.html
dev-lang/python-2.4.3-r1 does not actually support the tk USE flag!
when emerging the gimp:
fix at:
http://www.linuxforums.org/forum/gentoo-linux-help/75725-installing-gnome.html
USE="-tk" emerge -av python
and then emerge gimp (again)
Following: http://thomasgersdorf.com/linux/index.php/Gentoo_Linux_on_IBM_ThinkPad_T60:Fn-Keys
For power management/suspend to RAM and function keys use. No mention of AHCI in Thinkpad BIOS. Enabled sleep states under ACPI in stock 2.6.18 kernel. Emerged: acpid, and thinkpad - previously tpctl stuff also.
xxxxx: rc-update add acpid default
reboot and now: echo -n mem > /sys/power/state
suspends with use of crescent-moon function-F4 to wake up!
Loosely following excellent tutorial at:
http://www.kicadlib.org/Fichiers/:_Tutorial.pdf
as referenced from:
[question remains of how to adapt drawing for mandalas offering up GND, 5V, TX, RD serial circling the central processor - perhaps making use of graphic drawing (only of use on silkscreen layers) and print these at same time]
http://kicad.bokeoa.com/wiki/index.php/Mini_tutorial
http://www.neilvandyke.org/quack/
1] download and (require 'quack) in .emacs
http://www.neilvandyke.org/quack/quack.el
2] default fontlock for ;;; comments (three semicolons) is blue text-invisible bars. change this with:
(setq quack-fontify-threesemi-p nil)
3] Key bindings:
;; The key bindings that Quack adds to `scheme-mode' include: ;; ;; C-c C-q m View a manual in your Web browser. ;; C-c C-q k View the manual documentation for a keyword ;; (currently only works for PLT manuals). ;; C-c C-q s View an SRFI. (Scheme Requests for Implementation) ;; C-c C-q r Run an inferior Scheme process. ;; C-c C-q f Find a file using context of point for default. ;; C-c C-q l Toggle `lambda' syntax of `define'-like form. ;; C-c C-q t Tidy the formatting of the buffer.
Followed instructions at: http://bc.tech.coop/blog/060529.html
(using c key here within Conkeror to copy current link)
and:
http://conkeror.mozdev.org/installation.html
Numbered links: we simply enter the number
To find out more: C-h-i Man page (C- is control M- is meta) or C-h-b - list of all bindings
Simple stuff:
g - open new location
B and F - backwards and forwards
C-x-r-b - jump to bookmark
C-x-r-l - show all bookmarks
ESC to exit text box entry
and usual Emacs bindings - C-s for search which (in caret mode after hitting F7) also highlights and can thus be M-w into killring
One question: how do we access history... history.js?
1] Using old MAX3232 circuit from PIC times (see http://www.geocities.com/vsurducan/electro/PIC/pic84lcd.htm) with pin 11 of 3232 (T1IN) to TX pin 3 on ATmega, 12 (R1OUT) to RX pin 2.
2] 1 MHz is factory default internal oscillator frequency which we CAN change with Guido's prg_fusebit_uc script (1 MHz means we have to stay at 2400 baud and this is as set in minicom: 2400 8N1) - can only be changed without external oscillator upto 8 MHz
3] Sample serial writing code as follows:
#include <stdio.h>
#include <avr/io.h>
#include <inttypes.h>
#define F_CPU 1000000UL // 1 MHz
#include <avr/delay.h>
#define BAUD 2400
#define F_OSC 1000000 //default setting
#define UART_BAUD_RATE 2400
#define UART_BAUD_CALC(UART_BAUD_RATE,F_OSC) ((F_OSC)/((UART_BAUD_RATE)*16l)-1)
void init_uart(void)
{
// set baud rate
UBRRH = (uint8_t)(UART_BAUD_CALC(UART_BAUD_RATE,F_OSC)>>8);
UBRRL = (uint8_t)UART_BAUD_CALC(UART_BAUD_RATE,F_OSC);
// Enable receiver and transmitter; enable RX interrupt
UCSRB = (1<<RXEN) | (1<<TXEN);
//asynchronous 8N1
UCSRC = (1<<URSEL) | (3<<UCSZ0);
}
static int uart_putchar(char c, FILE *stream);
static FILE mystdout = FDEV_SETUP_STREAM(uart_putchar, NULL,_FDEV_SETUP_WRITE);
static int uart_putchar(char c, FILE *stream)
{
if (c == '\n')
uart_putchar('\r', stream);
loop_until_bit_is_set(UCSRA, UDRE);
UDR = c;
return 0;
}
int
main(void)
{
init_uart();
stdout = &mystdout;
while(1) printf("help!");
return 0;
}
4] serial echo (read/write echoes characters typed from miniterm based on wiring.c from Arduino):
http://1010.co.uk/testserial.c
5] Forgot that Emacs/Brood code of Tom Schouten's is all wrapped up in Forth... should be easy enough to use PLT or other Lisp/Scheme to wrap up communications with the scrying scheme board.
6] Next step is to use the LQFP32 packaged FT232BL (not R) board -
Kicad program for schematics looks good but we will have to modify the 232R component (both SMD and DIL ATmegas are available in additional libraries).
links:
Kicad: http://www.lis.inpg.fr/realise_au_lis/kicad/
Libraries: http://www.kicadlib.org/
(Oregano (limited as to component libraries), and Xcircuit also as possible schematic capture offerings).
to edit a schematic and generate a netlist before we make a PCB design in pcb (all GNU free software) - pcb is installed under Gentoo with seperate emerge command.
gschem (also gattrib for editing attributes of .sch files)
http://geda.seul.org/wiki/geda:gschem_ug
and the warmup:
http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/gschem-warmup.html
perhaps try CVS version
Progress so far:
What are the differences here between Default - reference component, embed component and component as individual objects (latter option seperates out and can thus be edited)?
Use reference I think...
ATmega8 component lacks VCC and GND and pin 1 is in an awkward place. First two remedied by modal operation/keystroke driven approach ... where we want pin ap keys and pull line with left mouse into body of chip. middle mouse to stop behaviour. an to add net/wire with similar results. select object with left mouse squaring over and add aa to attach/add attribute such as a pin number. ea to edit attributes of selected piece/element.
er to rotate elements, fs to save, z and Z to zoom, w to zoom next selected square, ve to view extents (?)
But how do we edit the ATmega8 stuff as it stands to switch pin 1?
(only problem is crashes on update)
see Wiki above:
Update Component (ep)
(we can use gattrib to edit attributes which are things like names/values/pin assignments but ...)
warmup above is a good place to start for simple operations.
note also:
it only makes sense to create pins while creating or editing symbol files...
note also url for gattrib: http://www.brorson.com/gEDA/gattrib/
ATmega8 platform, using free software tools, and based on Steele and Sussman's Design of Lisp-based Processors, and Abelson and Sussman's
;;;;EXPLICIT-CONTROL EVALUATOR FROM SECTION 5.4 OF ;;;; STRUCTURE AND INTERPRETATION OF COMPUTER PROGRAMS
;;SECTION 5.4.1 eval-dispatch (test (op self-evaluating?) (reg exp)) (branch (label ev-self-eval)) (test (op variable?) (reg exp)) (branch (label ev-variable)) (test (op quoted?) (reg exp)) (branch (label ev-quoted)) (test (op assignment?) (reg exp)) (branch (label ev-assignment)) (test (op definition?) (reg exp)) (branch (label ev-definition)) (test (op if?) (reg exp)) (branch (label ev-if)) (test (op lambda?) (reg exp)) (branch (label ev-lambda)) (test (op begin?) (reg exp)) (branch (label ev-begin)) (test (op application?) (reg exp)) (branch (label ev-application)) (goto (label unknown-expression-type))
also a pinch of Chaitin's C Lisp interpreter...
http://tuxgraphics.org/common/src2/article352/Makefile.html
in contrast Steele and Sussman make use of a 3 bit type field (plus 8 bits for the address) for 7 types (thus 256x 11 bit words)
#define CONSTANTL 0 #define CONSTANTS 1 #define VAREF 2 #define CC 3 #define PROC 4 #define COND 5 #define PROCEDURE 6 #define QUOTE 7
further storage notes (Steel/Sussman):
The method we use for implementing CAR, CDR and CONS is the usual one of using two consecutive words of memory to hold a list cell, the first being the cdr and the second the car, where each word of memory can hold a type field and an address field. The address part of the pointer is in turn the address within the linear memory of the record pointed to.
Abelson and Sussman use two vectors: the_cars and the_cdrs
http://mitpress.mit.edu/sicp/full-text/book/book-Z-H-33.html
We can use vectors to implement the basic pair structures required for a list-structured memory. Let us imagine that computer memory is divided into two vectors: the-cars and the-cdrs. We will represent list structure as follows: A pointer to a pair is an index into the two vectors. The car of the pair is the entry in the-cars with the designated index, and the cdr of the pair is the entry in the-cdrs with the designated index. We also need a representation for objects other than pairs (such as numbers and symbols) and a way to distinguish one kind of data from another. There are many methods of accomplishing this, but they all reduce to using typed pointers, that is, to extending the notion of “pointer” to include information on data type.7 The data type enables the system to distinguish a pointer to a pair (which consists of the “pair” data type and an index into the memory vectors) from pointers to other kinds of data (which consist of some other data type and whatever is being used to represent data of that type). Two data objects are considered to be the same (eq?) if their pointers are identical.
further:
The reader maintains a table, traditionally called the obarray, of all the symbols it has ever encountered. When the reader encounters a character string and is about to construct a symbol, it checks the obarray to see if it has ever before seen the same character string. If it has not, it uses the characters to construct a new symbol (a typed pointer to a new character sequence) and enters this pointer in the obarray. If the reader has seen the string before, it returns the symbol pointer stored in the obarray. This process of replacing character strings by unique pointers is called interning symbols.
cons as:
(perform (op vector-set!) (reg the-cars) (reg free) (reg <reg2>)) (perform (op vector-set!) (reg the-cdrs) (reg free) (reg <reg3>)) (assign <reg1> (reg free)) (assign free (op +) (reg free) (const 1))
further instruction summary:
A controller instruction in our register-machine language has one of the following forms, where each <inputi> is either (reg <register-name>) or (const <constant-value>). These instructions were introduced in section 5.1.1: (assign <register-name> (reg <register-name>)) (assign <register-name> (const <constant-value>)) (assign <register-name> (op <operation-name>) <input1> ... <inputn>) (perform (op <operation-name>) <input1> ... <inputn>) (test (op <operation-name>) <input1> ... <inputn>) (branch (label <label-name>)) (goto (label <label-name>)) The use of registers to hold labels was introduced in section 5.1.3: (assign <register-name> (label <label-name>)) (goto (reg <register-name>)) Instructions to use the stack were introduced in section 5.1.4: (save <register-name>)
http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-453.pdf
further Scheme research:
icbins: from http://www.accesscom.com/~darius/
with further interesting code there...
from the README from icbins:
Here we have an exercise in stripping a Lisp to barest essentials, dropping the host tether early, and repeatedly changing and rebuilding, to practice evolving a self-hosted system. Only the garbage collector and the lowest-level Lisp primitives are in C. The source is an order of magnitude smaller than the already-lightweight UTS's. You might find this of interest if you want to do similar exercises or if you'd just like to read a tiny Lisp system with no magic (small self-hosting Lisps typically rely on powerful primitives like READ, PRINT, and GC). This could be cut down further; hopefully I'll come back to it someday.
-a) checl we have ftdi_sio and usbserial modules built and loaded
a) we have the Arduino codebase
b) on Gentoo: emerge crossdev (had to first set PORTDIR_OVERLAY=/usr/portage in /etc/make.conf)
takes some time...
c) emerge avrdude programming utility AFTER b) succeeds
d) check out Makefile and modify as below
# Arduino makefile # # This makefile allows you to build sketches from the command line # without the Arduino environment (or Java). # # The Arduino environment does preliminary processing on a sketch before # compiling it. If you're using this makefile instead, you'll need to do # a few things differently: # # - Give your program's file a .cpp extension (e.g. foo.cpp). # # - Put this line at top of your code: #include <WProgram.h> # # - Write prototypes for all your functions (or define them before you # call them). A prototype declares the types of parameters a # function will take and what type of value it will return. This # means that you can have a call to a function before the definition # of the function. A function prototype looks like the first line of # the function, with a semi-colon at the end. For example: # int digitalRead(int pin); # # Instructions for using the makefile: # # 1. Copy this file into the folder with your sketch. # # 2. Below, modify the line containing "TARGET" to refer to the name of # of your program's file without an extension (e.g. TARGET = foo). # # 3. Modify the line containg "ARDUINO" to point the directory that # contains the Arduino core (for normal Arduino installations, this # is the lib/targets/arduino sub-directory). # # 4. Modify the line containing "PORT" to refer to the filename # representing the USB or serial connection to your Arduino board # (e.g. PORT = /dev/tty.USB0). If the exact name of this file # changes, you can use * as a wildcard (e.g. PORT = /dev/tty.USB*). # # 5. At the command line, change to the directory containing your # program's file and the makefile. # # 6. Type "make" and press enter to compile/verify your program. # # 7. Type "make upload", reset your Arduino board, and press enter to # upload your program to the Arduino board. # # $Id$
in:
http://1010.co.uk/arduino/Makefile
e) test code:
http://1010.co.uk/arduino/blink1.cpp
make: avr-g++: Command not found
next try: (after: http://www.arduino.cc/playground/Linux/Gentoo )
USE='-nocxx' emerge cross-avr/gcc cross-avr/avr-libc
make succeeds - we have a blink1.hex and so on
f) make upload
...
few changes to Makefile for avrdude and avrusb500 programmer, updated to new core Arduino necessitating more Makefile changes and now programs fine with 5v attached to ATmega on breadboard
g) pin mapping: http://www.arduino.cc/en/Hacking/
eg. digital pin 13 in blink LED example is true ATmega8 pin 19
// On the Arduino board, digital pins are also used // for the analog output (software PWM). Analog input // pins are a separate set. // ATMEL ATMEGA8 / ARDUINO // // +-\/-+ // PC6 1| |28 PC5 (AI 5) // (D 0) PD0 2| |27 PC4 (AI 4) // (D 1) PD1 3| |26 PC3 (AI 3) // (D 2) PD2 4| |25 PC2 (AI 2) // (D 3) PD3 5| |24 PC1 (AI 1) // (D 4) PD4 6| |23 PC0 (AI 0) // VCC 7| |22 GND // GND 8| |21 AREF // PB6 9| |20 AVCC // PB7 10| |19 PB5 (D 13) // (D 5) PD5 11| |18 PB4 (D 12) // (D 6) PD6 12| |17 PB3 (D 11) PWM // (D 7) PD7 13| |16 PB2 (D 10) PWM // (D 8) PB0 14| |15 PB1 (D 9) PWM // +----+
h) one problem with Scheme/Arduino plan is presented by wiring.c which wraps setup and loop into main function.. but we could easily replace this
in x86 assembly
http://www.stripedgazelle.org/joey/dream.html
note:
The design for the 'dream' Scheme interpreter began with the design given in Abelson and Sussman's Structure and Interpretation of Computer Programs.
also:
again, chapter five of SICP:
from: http://www.ida.liu.se/~tobnu/scheme2llvm/
This is a small (about 1K lines) self applicable scheme toy compiler which compiles to C-code, and a version that compiles to LLVM with the types fixnum, symbols, strings, functions and vectors (cons cells are seen as vectors of size 2).
and:
The code is quite similar to the code in SICP (Structure and Interpretation of Computer Programs), chapter five, with the difference that it implements the extra functionality that SICP assumes that the explicit control evaluator (virtual machine) already have. Much functionality of the compiler is implemented in a subset of scheme, c-defines (llvm-defines), which are compiled to C-functions (llvm functions).
code for SICP at:
http://mitpress.mit.edu/sicp/code/index.html
[also within alice/kodiak.lisp representation import/export of worlds]
also as performative expansion of xxxxx_at_interface
on the one hand, now that which we can call alice, the environment based on the existent (GNU Emacs and beyond)
on the other hand the existent cpu or hardware (either as fpga or using the ATMega (see cpu link)
environment and series of (preferably networked, interpretative, bit spouting) CPUs within the black marias cpu_model connected by way of serial (and thus USB, or Ethernet using the ENC28J60 from Microchip)
also interface to paper circuits.
Film before Film: What Really Happened Between the Images? (1986) by Werner Nekes
(position of Edison and Black Maria studio within such a history)
Universal Dovetailer. Generation of FPGA HDL. Language generation.
Code stepper.
import/export of both evaluatable code and code environments. OSC.
continuations. leakage. representation (our language finally).
Chapter 5: Computing with Register Machines
walking through a Scheme interpreter and compiler for hypothetical (simulated in this instance) stack-based register machine (minus (as simulated in Scheme) various primitive operations such as car, cons))
for such primitives (and a similar implementation) also see:
http://www.frank-buss.de/lispcpu/lispcpu.lisp.txt
(defconstant primitives '#(+ - < > <= >= /= = * set quote setq defun progn get-time set-time set-led get-led while cons car cdr if))
Storage of car, cdr structures is outlined in section 5.3 p533. also garbage collection
towards lispcpu, also perhaps ATMega interpreter/compiler
Lets you place hyperlinks and shell/tcl/TeX/etc code inside plain text files.
from:
http://www.mat.puc-rio.br/~edrx/emacs.html
note also:
Emacs and eev, or: How to Automate Almost Everything
http://angg.twu.net/eev-article.html
with possible use for promiscuOS see:
http://angg.twu.net/eev-article.html#.channels
The way that we saw to send commands to a shell is in two steps: first we use M-x eev in Emacs to send a block of commands, and then we run `ee' at the shell to make it receive these commands. But there is also a way to create shells that listen not only to the keyboard for their input, but also to certain communication channels; by making Emacs send commands through these communication channels we can skip the step of going to the shell and typing `ee' --- the commands are received immediately.
(making use of netcat - netcat as key possible tool for promiscuOS)
OpenGL renderer string: ATI MOBILITY FireGL V5200 Pentium 4 (SSE2) (FireGL) (GNU_ICD)
but also needed to rmmod and then modprobe:
ipw3945 for wireless
vague notes: xterm -ls option to read .bash_rc, win32codecs in USE flags for streaming firefox/mms/wmv:
with thanks to:
http://zerlinna.blogweb.de/archives/73-Watching-Video-streams-mms-and-rtsp-protocol.html
unrelated: at 23c3: http://www.lochraster.org/etherrape/
ethernet for the atmega...
Gentoo install functioning. Notes:
wired untested. wireless working
echo "x11-drivers/ati-drivers ~x86" >> /etc/portage/package.keywords
using fglrx in xorg.conf but no hardware OpenGL as first complained of lack of fglrx_dri.so in /usr/lib/dri - made this directory and copied across but no luck (undefined symobols there) - to be fixed
unrelated: to check out clfswm Lisp window manager
we need fltk as use flag in /etc/make.conf
# These settings were set by the catalyst build script that automatically built this stage
# Please consult /etc/make.conf.example for a more detailed example
CFLAGS="-march=prescott -O3 -mtune=i686 -msse3 -fomit-frame-pointer -pipe"
CHOST="i386-pc-linux-gnu"
CXXFLAGS="${CFLAGS}"
VIDEO_CARDS="fglrx vesa fbdev"
INPUT_DEVICES="keyboard mouse synaptics"
FEATURES="sandbox ccache distlocks autoaddcvs parallel-fetch"
MAKEOPTS="-j3"
GENTOO_MIRRORS="ftp://ftp.tu-clausthal.de/pub/linux/gentoo http://distfiles.gentoo.org http://www.ibiblio.org/pub/Linux/distributions/gentoo"
USE="ibm dvd alsa cdr fltk"
SYNC="rsync://rsync.gentoo.org/gentoo-portage"
links:
and:
http://bellet.info/laptop/t60p.html
Gentoo as preferable:
http://buzzy.tesuji.org/thinkpad_t60p.html
and:
http://www.thinkwiki.org/wiki/Installation_instructions_for_the_ThinkPad_T60p:Kernel_Settings
potential installation from Ubuntu LiveCD 6.10 which recognises Ethernet and Wireless so far:
http://www.gentoo.org/doc/en/altinstall.xml (Knoppix here).
Using the AVR programmer USB, stk500 V2 compatible from:
http://shop.tuxgraphics.org/electronic/microcontroller.html?id=2b93dd
(with thanks to Guido)
Further documentation online at:
http://www.tuxgraphics.org/electronics/200510/article05101.shtml
and also for avr-gcc:
http://www.tuxgraphics.org/electronics/200411/article352.shtml
notes:
mkdir /tmp/mnt
mount -o loop /mnt/cdrom/KNOPPIX/tgr/avr.img /tmp/mnt
cd /tmp/mnt
find avr* | cpio -dump /usr/local/
cd ; umount /tmp/mnt
# and add bin to PATH.
PATH=${PATH}:/usr/local/avr/bin/
export PATH
Makefile is at:
http://main.linuxfocus.org/common/src2/article352/Makefile.html
and uses avr-gcc, avr-objcopy and prg_load_uc shell script which references:
avrdude -p m8 -c avrusb500 -e -U flash:w:"$pfile"
prg_fusebit_uc is also used to "read and write fuse bits of the atmega8"
AvrUsb500 Programmer Kit
mentioned below (notes on this to follow).
http://www.arduino.cc/playground/uploads/Learning/Makefile
# This makefile allows you to build sketches from the command line # without the Arduino environment (or Java). # # The Arduino environment does preliminary processing on a sketch before # compiling it. If you're using this makefile instead, you'll need to do # a few things differently: #
then compiles and links with Arduino library .c (and .cpp) files
and further compiles using avr-gcc, avr-objcopy and so on and uploads with avrdude.
or rather:
an interpreter or vm (virtual machine) in flash
http://amforth.sourceforge.net/
as in:
amforth is a distribution of Forth running on the AVR ATmega microcontroller. Once put into flash, it needs only a serial connection to the host computer. New words are compiled directly into flash, thus extending the dictionary immediately. It is ans94 Forth oriented with some minor exclusions and a few words from the extension word sets. It is written in assembly language and Forth itself. The main development uses ATmega8 and ATmega32 controllers; other ATmega controllers should work with small adjustments.
http://1010.co.uk/audioprinter.c
gcc audioprinter.c -o audioprinter cat /dev/mem | ./audioprinter
Following Pascal Bourguignon's advice (http://www.informatimago.com/linux/emacs-on-user-mode-linux.html).
A few points:
(global-set-key "^\" 'keyboard-quit) ;; strangely, C-g does not work.
from /emacs/.emacs
emacs: Terminal type linux is not defined.
mkdir -p /emacs/usr/share/terminfo cp -R /usr/share/terminfo/* /emacs/usr/share/terminfo/
1] No go with slackware 7.1 rootfs downloaded.
2] re-attempt Emacs on UML with present 21.4 source. In final linking now we have a segmentation fault:
Dumping under names emacs and emacs-21.4.1 make[1]: *** [emacs] Segmentation fault make[1]: *** Deleting file `emacs'
same as for 21.3 source... and with or without static flags ...
3] now thanks to:
http://article.gmane.org/gmane.emacs.devel/17457
[Re: Unable to bootstrap GNU Emacs 21.3 (SOLVED)]
and no thanks to:
"[...] Exec-shield is a security-enhancing modification to the Linux kernel that makes large parts of specially-marked programs _ including their stack _ not executable. This can reduce the potential damage of some security holes. Exec-shield is related to the older "non-exec stack patch" but has the potential to provide greater protection.
Exec-shield can also randomize the virtual memory addresses at which certain binaries are loaded. This randomized VM mapping makes it more difficult for a malicious application to improperly access code or data based on knowledge of the code or data's virtual address.
[...]
Exec-shield functionality is available only to binaries that have been built (and marked) using the toolchain (compiler, assembler, linker) available with Fedora [...]"
turn it off:
1] kernel level (which could also include some kind of dissolution at the network level).
2] application or user level -
and the 1] 2] boundary as leakage = UML (User Mode Linux) - kernel as userland app
quick UML notes:
1] grabbed a 2.6.19 kernel from: http://ftp.ca.kernel.org/linux/kernel/v2.6/
bunzip2 linux-2.6.19.tar.bz2 tar xvf linux-2.6.19.tar cd linux-2.6.19 make defconfig ARCH=um ## default configuration make ARCH=um
2] Results in... linux. Then run ./linux
3] No filesystem!
So, relying on [[http://www.informatimago.com/linux/emacs-on-user-mode-linux.html][Emacs on UML]] we can make a filesystem as follows:
cd ~/uml dd if=/dev/zero of=root_fs_emacs bs=1k count=200k yes y|mke2fs root_fs_emacs # note that yes command outputs string y repeatedly mkdir /emacs mount -o loop root_fs_emacs /emacs cd /emacs ln -s . emacs # we create this link to simplify config --prefix of emacs cp -a /dev dev # we boldly copy the whole /dev mkdir etc sbin tmp # some other directories not installed by emacs cat >etc/fstab <<EOF /dev/ubd0 / ext2 defaults 0 1 EOF
4] Following steps to statically link Emacs-22 fails:
: warning: Using 'getservbyname' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking /usr/lib/gcc/i386-redhat-linux/3.4.2/../../../libc.a(mktime.o)(.rodata+0x0): multiple definition of `__mon_yday' mktime.o(.rodata+0x0): first defined here /usr/lib/gcc/i386-redhat-linux/3.4.2/../../../libc.a(mktime.o)(.text+0x0): In function `__mktime_internal': : multiple definition of `__mktime_internal' mktime.o(.text+0x373): first defined here /usr/bin/ld: Warning: size of symbol `__mktime_internal' changed from 1502 in mktime.o to 2546 in /usr/lib/gcc/i386-redhat-linux/3.4.2/../../../libc.a(mktime.o) collect2: ld returned 1 exit status make[1]: *** [temacs] Error 1 make[1]: Leaving directory `/root/emacs-22.0.91/src' make: *** [src] Error 2
5] Filesystems from uml/sourceforge eg.tomsrtbt fail at INIT or elsewhere - construct from scratch.
1] sans TCP:
see: httpd.el -- a web server in Emacs Lisp
at: http://www.chez.com/emarsden/downloads/
notes:
:: Since Emacs does not (yet!) provide server sockets, you ;; need a helper program to bind to the socket and forward requests. ;; There are two ways of doing this: use a service like inetd to ;; launch a fresh emacs instance for each incoming request, or use a ;; program which forwards requests via gnuserv. The second method ;; obviously provides better performance.
eg:
;; 8080 stream tcp nowait.10000 nobody /usr/bin/emacs emacs -batch \ ;; -l /path/to/httpd.el -f httpd-serve
or use httpd-serve Python script... (from where?)
or see:
muse-http.el file that can turn Emacs into a webserver, much like the emacs-wiki-httpd.el module, except that it doesn't need an external Python script.
muse-http handles requests by way of httpd.el later version:
http://sacha.free.net.ph/notebook/emacs/muse/httpd.el
with lines:
(defun httpd-start (&optional port) (interactive (list (read-input "Serve Web requests on port: " "8080"))) (if (null port) (setq port 8080) (if (stringp port) (setq port (string-to-int port)))) (if httpd-process (delete-process httpd-process)) (setq httpd-process (open-network-stream-server "httpd" (generate-new-buffer "httpd") port nil 'httpd-serve)) (if (eq (process-status httpd-process) 'listen) (message "httpd.el is listening on port %d" port)))see also:
http://www.emacswiki.org/cgi-bin/wiki/rcirc.el
2] In GNU Emacs reference manual:
Emacs Lisp programs can open TCP network connections to other processes on the same machine or other machines. A network connection is handled by Lisp much like a subprocess, and is represented by a process object. However, the process you are communicating with is not a child of the Emacs process, so you can't kill it or send it signals. All you can do is send and receive data. delete-process closes the connection, but does not kill the process at the other end; that process must decide what to do about closure of the connection.
3] Gnuclient and gnuserv:
Gnuserv: It allows arbitrary Emacs Lisp commands to be sent to an Emacs process running either on the local machine or on another machine on the network.
http://linuxgazette.net/issue29/marsden.html
4] ebby - shared Emacs buffers for collaborative editing (no link)
(on this thread:
http://technomancy.us/blog/post/45 and:
http://bc.tech.coop/blog/060509.html)
and thus:
5] Distel: http://bc.tech.coop/blog/060111.html
TODO::
what is already in planner/emacs-wiki to make such grouping possible?
(add-to-list 'remember-planner-append-hook 'planner-rss-add-note t)
called in: remember-planner-append (&optional page) within remember/remember-planner.el
deosn't work. we need to know what exactly is a note.
see ~/elisp/snuff.el:
(emacs-wiki-published-name (planner-note-page info))
need to know how pages are organised
simple version control
rcsintro - introduction to RCS commands
DESCRIPTION
The Revision Control System (RCS) manages multiple revisions of files. RCS automates the storing, retrieval, logging, identification, and merging of revisions. RCS is useful for text that is revised frequently, for example programs, documentation, graphics, papers, and form letters.
The basic user interface is extremely simple. The novice only needs to learn two commands: ci(1) and co(1). ci, short for `check in', deposits the contents of a file into an archival file called an RCS file. An RCS file contains all revisions of a particular file. co, short for `check out', retrieves revisions from an RCS file.
RCS as created directory under project sub-directory
rcsmerge is used in our xxxxx_publication version control text:
rcsmerge -p -A -r1.1 -r1.6 alice > version_control
how this could be integrated with emacs-wiki/planner for automatic generation of merge files
SBUML is an extension to User-mode Linux(UML) that can save complete Linux runtime states in mid-execution(including all hard disks, devices, processes, and kernel space). The same state can be restored at a later time on the same PC, or migrated to another PC. The states can be delta compressed to a few megabytes or less, making it practical to download running Linux machines from websites.
functionality to Emacs/Emacs-wiki:
1] Helpful here is C-x h k (in this case, otherwise C-h k) to see what function keystroke calls, or use M-x apropos and in either case browse to underlined function and hit return to jump to code.
2] If we then need to view code for another function at point then we can use C-x h f (in this case: in other C-h f).
3] Looking at how to read from minibuffer and use in interactive mode in Emacs Lisp:
http://xahlee.org/elisp/Using-Interactive.html
4] Final code:
(defun cat-add (&optional string) (interactive (let ((string (read-from-minibuffer "mytag:"))) (list string))) (insert "<category domain=\"http://1010.co.uk\">" string "</category>"))result - but we just want to pass to rss feed:
<category domain="http://1010.co.uk">emacs</category>
but in rss it should come just before
</item>tag
problem is rss is parsed/created at last moment of publishing - we could search and get it to insert this in the right place
by way of http://bc.tech.coop/blog/061119.html
mosref running with mosquito-lisp
TODO for data_radio project and also promiscuOS
also to note:
http://en.wikipedia.org/wiki/WASTE
and (for promiscuOS): http://www.vanheusden.com/listenpipe/
Listenpipe can be used to sit between 2 applications that are interfaced with pipes. It will pass through data as is but also store what is send/received in a logfile as well.
for leaking pipe code
by way of:
http://bc.tech.coop/blog/061115.html
MzScheme on OSKit: http://download.plt-scheme.org/mzscheme/mz-103p1-bin-i386-kernel-tgz.html
Emacs standing alone on a Linux Kernel: http://www.informatimago.com/linux/emacs-on-user-mode-linux.html
some possible uses for promiscuOS
first prototype:
1] GNUS related: http://www.zarb.org/~gc/html/howto-adopt-gnus.html
2] For planned noise/re-purpose workshop in Berlin:
Mix 555 with finger timing addition, 40106 and transistors on etched board with possile connections - or a series of modules, the transistor NAND gate also.
[paper radio receiver - question of the diode]
3] Also possibly for workshop - paper noise circuit/computer with capacitance between traced sheets:
Wide frequency range oscillators with homemade variable capacitor:
http://home.earthlink.net/~lenyr/varelec.htm
4] Planned workshops: Python, PD, electronics, PIC, VLF, TV transmission, FPGA, Pure:dyne, goto10
with advice from:
http://lifelogs.com/spam/spam.html
and:
http://paste.lisp.org/display/4589
(setq spam-use-BBDB nil
spam-use-stat t
spam-split-group "mail.spam"
spam-stat-split-fancy-spam-group "mail.spam"
spam-install-hooks t)
(setq nnmail-split-fancy
`(| (: spam-split)
;; insert usual split rules in split-fancy syntax
"mail.misc"))
(from http://sacha.free.net.ph/notebook/emacs/planner-config.el )
Evaluated http://elisp.info/package/rss-helper/rss-helper.el
and used rss-helper-gnus-subscribe
which subscribes gnus to rss feed by way of url...
but gives no such newsgroup error after specify the title.
By way of:
http://www.emacswiki.org/cgi-bin/wiki/
technique as follows works:
from Group buffer: G m and group name (eg. 1010test) with nnrss as backend, then when we ENTER for the first time, we are prompted for a URL to search for the feed...
the result looks like:
. [ ?: nobody ] http://www.voti.nl/blink/index_1.html 17:28 . [ ?: nobody ] 16:02 . [ ?: nobody ] link to interface and society slides: 12:54 . [ ?: nobody ] interface and society presentation: 03:00 R. [ ?: nobody ] 03:11
as PIC test reference
1] Kasparov chess interface:
8x8 touch switch interface potentially for FPGA.
we have 8+8 wires from switches - these are pulled high (6v) to low (0.5v) when switched
2] 4016/4066 digital switch tests:
On breadboard, we can switch an (audio) signal (I/O (Y0, Z0) on pins 1 and 2, enable E0 on 13, 6v on 14 and GND on 7). E0 is tied with a 10K pull down resistor to GND so that bringing E0 high will allow Y0, Z0 current.
3] Transistor regulating voltage:
2N3904. CBE viewed upright from back (non-flat).
CV is by way of 10K resistor to base, emitter to output and by way of 4.7K incoming signal.
4] Further brood/cat/purrr meanderings:
a) Latest darcs pull doesn't seem to work, complains of unbound variable for -e purrr and some other problem for emacs cat.el which in principle seems to work well with older version. M-x cat after eval-buffer.
b) Following new steps with previous brood pull (pre-piksel):
(18f sheepsint) restore (after downloading: http://goto10.org/~tom/18f/sheepsint-20060914.tar.gz )
then connect-default...:
error: (not-found connect-default)
still no ping...
c) Troubleshooting serial connection. Incoming serial (black RX on pin 10) seems fine. Outgoing from pin 9 of PIC18F1220 not. Tested with different PICs, MAX3232 still nothing. Sometimed random characters (numbers) from a ping.
In theory:
1] export XILINX=~/Xilinx // where we have our Xilinx distribution
2] ~/Xilinx/bin/lin/promgen -u 0 ~/piksel/fpga_src/tutorail2/tutorial.bit -p exo -s 2048 // make EXO file from our VGA project bitfile
3] xsload -b xsa-50 -flash ~/piksel/fpga_src/tutorail2/tutorial.exo // downloads to the board
to test the last step:...
TESTED on T20 (though strangely xstest fails)
[ see further: http://www.xess.com/manuals/xstools-v4_0.pdf ]
(setq planner-rss-base-url "http://1010.co.uk/")
test3
is a sophisticated electrical CAD system that can handle many forms of circuit design, including:
http://www.gnu.org/software/electric/
http://www.staticfreesoft.com/jmanual/
other schematic-oriented free softwares:
gschem: http://www.geda.seul.org/screenshots/index.html and PCB:
http://www.geda.seul.org/tools/pcb/index.html
see also http://www.geda.seul.org/
http://libarynth.org/cgi-bin/view/Libarynth/
see:
http://www.iro.umontreal.ca/~feeley/
and PICBIT: A Scheme System for the PIC Microcontroller
http://www.iro.umontreal.ca/~feeley/papers/sw03.pdf
also ref. Otto Roessler crash transcript at:
http://libarynth.org/cgi-bin/view/Libarynth/:2005
http://www.cs.utexas.edu/users/moore/acl2/v3-0/distrib/acl2-sources/books/workshops/1999/vhdl/
quote:
This directory contains the supporting files for Chapter 11, "Using Macros to Mimic VHDL", by Dominique Borrione, Philippe Georgelin, and Vanderlei Rodrigues, in "Computer-Aided Reasoning: ACL2 Case Studies", edited by M. Kaufmann, P. Manolios, J Moore (Kluwer, 2000, p.167-182).
and:
File fact.lisp is the example in Figure 1. It is the description of the circuit that computes the factorial function, using two concurrent processes. It uses the macros defined in the preceding file.
XSTEND and own FPGA expansion board pin details:
own interface:
8 IN 8 OUT (IN into voltage divider and both by way of 74hc245 transceiver
TOP (4 pin VGA interface)
1: GND
2: 5V
3: VSYNC
4: HSYNC
FPGA XSTEND: ref to FPGA pins (xsa-200/xsa-3s1000):
VERTICAL LINE FROM TOP:
0-7: IN
0: A5/F15
1: F14/P12
2: P9/J1
3: R9/H1
4: T9/H3
5: T7/G2
6: B9/K15
7: A9/K16
0-7: OUT
0: M7/E2
1: R6/E1
2: N7/F3
3: P7/F2
4: R7/G4
5: T14/G3
6: P8/G1
7: T8/H4
(both above as bi-directional I/O ports - extra 16 IN should be available)
0-7: MISC
1: GND
2: 5V
3: VSYNC
4: HYSNC
but all inputs must be tied down (by connection to FPGA)
http://www.stanford.edu/class/ee183/verilog/183lib.v
with 10K resistors on inputs, 5.6K 5v to collector
the NAND inputs must normally be logic 1 to avoid affecting the latching action, the inputs are considered to be inverted in this circuit.
it is forbidden to have both inputs at a logic 0 level at the same time. That state will force both outputs to a logic 1, overriding the feedback latching action. In this condition, whichever input goes to logic 1 first will lose control, while the other input (still at logic 0) controls the resulting state of the latch. If both inputs go to logic 1 simultaneously, the result is a "race" condition, and the final state of the latch cannot be determined ahead of time.
http://www.play-hookey.com/digital/rs_nand_latch.html again
Pyastra: python assembler translator (for PIC micros):
http://pyastra.sourceforge.net/
To construct components from HDL description in Xilinx WebPAck ISE:
Design utilities -> create schematic symbol
[further notes on Steele and Sussman's LispCPU]
1] Microcode:
quote [p35]:
Each of the two parts, EVAL and GC, is itself divided into two parts: registers and controller. The registers provide storage for type/pointer words, and are connected by a common bus in each part. Each controller is a finite-state machine implemented as a PLA, plus some random logic. Each PLA is organised as a micro-code ROM, addressed by a "Micro-PC" and yielding a set of control signals, including register controls and a new micro_PC indicating the next state.
signals enumerated on p36
p39. [SIMPLE Microcode] There are five kinds of operation EVAL can request from the GC (which give EVAL the step-eval signal to advance):
NOP, CAR/CDR, CONS/NCONS, RPLACD and load/store Q (one of GC's registers).
p40:
[quote]
The CONS operation accepts a car pointer from the E bus, takes the contents of Q to be the cdr pointer and then allocates a new two-word cell containing the car and cdr. A pointer to the result, with type 0 (list) is left in Q.
The Microcoded PLA is produced by software from the assembly listing (p48+) produced by the micro-assembler software from the listing (p43+)
2] The register cell
[p63]
One-bit register cell. The signal LD during O/1 loads the cell from the data bus. The signal RD during O/1 drives the bus from the cell. The cell is refreshed during O/2.
the high- low- level overlap we are interested in
in terms of a methodology of description (code, the diagram, a description of behaviour, software generation of HDL)
after: Design of LISP-Based processors ... or, LAMBDA The Ultimate Opcode
Guy Steele and Gerald Sussman
(http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf ) 1979, MIT
1] Architecture reflectes language structure
2] The overlap of high level and machine language is also dictated by necessity to manipulate program as data
3] Programs are represented as nested Lisp data structures -> as a tree of linked records subject to a recursive tree walk
4] Lists are represented by records each of which contains 2 pointers to other records - car and cdr
5] The type field associated with each pointer is used to encode opcodes and return addresses
6] p17 implementation:
7] Two consecutive words of memory hold a list cell - each word can hold a type field and an address field (an address referenced within linear memory)
8] The evaluator and the storage manager as individual processors each with a state machine controller and a set of registers
contents of any register is address field and type field
9] p32 evaluation and procedure call (type 6):
We have a 3-bit type field which provides 8 opcodes (recall 7 as quotation) - address part of a word has different function depending on type (6 is procedure call).
quote:
The evaluation of type 4 (procedure) results in a pointer to the newly allocated word pair. This pointer has type 3 (closure). The car of the pair contains the cdr of the procedure: this is the code body of the procedure. The cdr of the pair contains the current environment.
and:
A procedure call (type 6) is the most complicated... It is a list of indefinite length, chained together by cdr pointers. Each cdr pointer except the last MUST have type 0 (list). The last cdr pointer should have a zero address and a non-ZERO type. This last type specifies the operation to be performed. In CDRing down the list, SIMPLE evaluates each of the expressions in the car, saving the resulting values. These values are available as arguments to the operation to be performed.
operations in tyoe here such as car, cdr, cons, atom, progn, list and funcall
10] further question of recursion in hardware by way of closures:
A closure combines the code of a function with a special lexical environment bound to that function (scope).
5v (TTL a la 74xxxx) to 3.3v (FPGA)
The second thing to do is to insert resistors between the output signals of your 5V circuitry and the gluion's 3.3V inputs. 1k Ohm will do. Furthermore you will need a clamping diode with the anode at your input pin, the cathode tied to 3.3V.
also for matrix 8x8 (chess computer interface):
Some details on the above schematic for the curious: the basic principle of a switch matrix is time-division multiplexing. This is denoted by the pulse diagrams to the left side of the SMR pins where you can see that first SMR0 is pulled low while all other SMR lines are kept high. The system then checks at which SMC pins the pulse arrives, i.e. it now knows which buttons of row 0 are held down. The process is then repeated for each row before re-starting the cycle. This is done at such a high frequency that even the shortest button closure is registered.
The resistors above the SMC pins are internal to the FPGA, i.e. you don't have to supply them yourself. They were implemented to keep the inputs from floating. As a consequence the Switch Matrix is operating in negated mode, i.e. diodes being "reversed" and pulses going down instead of up. However, this should be of no concern to the user, as long as you connect the diodes as shown above.
see: http://www.glui.de/prod/gluion/manual/gManMain.html
using FPGA for H and V sync
(for RGB from Schmitt triggers remember to link GND from board(s) to box)
~/piksel/fpga_src/tutorail2/
latest .bit as tutorial.bit
FPGA Pins:
Hsync: 85 out
Vsync: 86 out
Input: Output: all bi-directional
0: 67 12
1: 39 13
2: 44 19
3: 46 20
4: 49 21
5: 57 22
6: 60 23
7: 62 26
1] Salo (or any other film) modelled as/in Lisp process with a necessary overlap of (changed) language, structure and quotation - active language ie. that we do not simply slot the events of the film into an established framework but rather map the processes as/and characters.
2]. FPGA extension board tests (+5v) + VGA (need more headers). also test chess matrix interface. PCB photoboards. Daniel Paul Schreber. Notes...
3] Lisp cell structure to expand on. in the CPU/FPGA. a symbol
4] To collate the instruction set and the fictional data sheet with addition now of Alice instructions - Alice data bus or transmission lines ( And after that other voices went on (What a number of people there are in the carriage!' thought Alice), saying, `She must go by post, as she's got a head on her -- ' `She must be sent as a message by the telegraph -- ' )...
instructions such as "off with her head" stack head. Salo quotation cells
If brittle. Uses 74LS245 8 Bus-Transceiver for input (but 245 also can be controlled as to direction.) - potential expansion board for FPGA or schmitt triggers using these
74LS374 8 bit D-register for output
+ other logic including 74LS139 2 bit de-multiplexer
TODO: voltage dividers and possible 245s for FPGA extension board
1) J.G Ballard's Atrocity Exhibition as closest to an (expanded, to some extent architectural) instruction set for an imaginary CPU.
yet to be codified
2) circular memory (bubble is similar).
(to test IOE expansion board)
Of interest here is the ghosting of registers:
There are two sets of six general purpose registers + accumulator and flag registers (duplicate set swopped (values exchanged) by the Exchange instruction) - "The alternate set allows operation in foreground-background mode or it may be reserved for very fast interrupt response."
(From Z80 product specification).
Further 16 -bit wide registers for index, stack pointer,program counter and split (down to 8-bit) interrupt and memory reset. Also interrupt and other flip-flops.
Instruction set:
divided into categories, and described as to mnemonics and opcode
also addressing mode
LD r,r'
EX DE,HL
INC r
NEG
NOP
ADD HL, ss
RLC r
BIT b, r
JP nn
CALL nn
IN A, (n)
see also: http://www.z80.info/#BASICS_INST
also:
Binary form of opcodes
Example: LD r,r'
the 8-bit binary opcode is
01dddsss
...where "ddd" is a three-bit field specifying the destination,
and "sss" is a three-bit field specifying the source.
is shown below as
r r'
01 xxx xxx
overmapping Salo/Sadean life coding onto instruction sets
in the first instance (or with Alice/Looking Glass/Ripper whole codified mapping - to commence in process).
to start by way of circles as registers: circle of manias, circle of shit, circle of blood (with Pasolini borrowing from Dante's nine circles of hell).
As artefacts for piksel. NDR system (German) from GRAF electronics.
Working with HEXIO2 display and data entry board, SBC3 (Single board computer) main Z80 board with EPROM (for example programs and CP/M) and 8K RAM. Also IOE extension board with additional logic and prototyping area.
To program:
1] Press SPE. Type in memory address (default for code is 8100). Hit CR. Type in hexadecimal for translated opcode/addressee. + to advance in memory.
2] START followed by start address to commence execution.
We can also examine registers, ports, step through program and so on.
1] Do we use Schmitt triggers on I/O to provide logic levels (and then limit these with series resistor or voltage divider)?
2] or just use voltage divider in concert with 100 Ohm current limiter
3] or present both options on an expansion board
Test this for VGA throughput!
/usr/bin/mencoder -of mpeg -mpegopts format=dvd -srate 48000 -ofps 25 \ -ovc lavc -oac lavc -lavcopts \ vcodec=mpeg2video:vrc_buf_size=1835:keyint=15:vrc_maxrate=9800:vbitrate=4900:aspect=16/9:acodec=ac3:abitrate=192 \ test.avi -o test.mpeg2
Its expansion into an 8 bit register (8 simultaneously clocked flip-flops)
or, a 4-bit shift register (data is passed along the chain)
or, a 4 bit counter
1] Can we directly wire analogue signal across the FPGA (say from I/O pin to VGA resistors/input)?:
Using wires and assign. To test.
2] Limiting and/or isolation. All voltages < 3.3v
3] 8 bit to 8 bit - 8 cells or 8x8 matrix of cells. life, cellular automata - that matrix.
Replicated cells composed of micro-structures below:
4] Structures and/or instructions for the CPU:
a) Large Glass - Duchamp. A mechanism (in space).
b) The boudoir/bedroom. A singular eye.
c) Simulated world (billiard ball universe). Kopf. Mushroom cloud neurons.
d) Doubling/ghosting of gates - twinned Alice CPU
e) Further: a passage, quotation, representation. observer embedded
5] Gate diagrams (NOT, AND, NAND, OR, NOR) as artefacts:
6] Gate as switch. see diagrams for transistor multiplex switch symbol in a circle.
Switching across our non-optimal models.
Elaboration of physical circuits (for playing) alongside FPGA - headers and pin extension, break out. Coincident also with software (Lisp) simulation. Machine describing itself, its own coincident layers of active voltage. Reference SICP:
A Simulator for Digital Circuits:
http://mitpress.mit.edu/sicp/full-text/sicp/book/node64.html
and streams: http://mitpress.mit.edu/sicp/full-text/sicp/book/node72.html
7] S/R set-reset flip-flop:
for HDL see: http://myhdl.jandecaluwe.com/doku.php/cookbook:ff
D. flip-flop:
Both based on the NAND gate - a principle of exclusion of the twin (the equivalent/identical binary pair - two ones). Thus of difference enabling a memory. Memory in an active circuit dependent always on current flow. In D flip-flop the clock line straddles the doubled NAND, with a replication of the signal enabling the difference.
Two snakes bite each others tails.
http://www.geocities.com/:/2072/cpudes.htm
and
http://www.geocities.com/:/2072/verilog.htm
see also:
http://www.mindspring.com/~tcoonan/risc8doc.html
http://www.mindspring.com/~tcoonan/pic.v
Using code from:
http://www.stanford.edu/class/ee183/handouts.shtml
we can do very simple sync and when asserted (when we can write as is visible) we can write 6 bits of piksel data (RGB 2 bits for each). next step generate video or connect prototype board pins direct to VGA (thru FPGA? as it has its own 33ohm series resistors or we just send sync out to proto pins and hardwire VGA)
ultimate black box:
dual CPUs ghosted...
as per waves and xxxxx_at_piksel:
After Artaud, the CPU (central processing unit) and its double mimes The Theatre and its Double. On the one hand, there is the System or entropic operation of a necessarily cynical machine for living, an atrocity exhibition, on the other hand the specification of an artistic CPU for life coding.
This is precisely the twinned instruction set we need to devise for multiple CPUs exposed as our 8 bits (one/zero), our pulses for an architecture which is somehow composed from diagrams.
we can just generate sync from say PIC based sync code
http://yusoft.kulichki.net/english/pic/my_proj.htm
and run straight into voltage dividers to VGA connector as below
FPGA switches itself
concurrent exposed communicative (promiscuous) (instruction?) modules
exposed by way of PWM or rather single bits which can then be output as audio or as video / composite (with sync generation in software - we have an NTSC example but colour PAL is more complex - also using small resistor ladder to output) or VGA (we have vgahdl example code which looks quite simple)
and also using voltage dividers provided by resistors:
quote
Pins 13 and 14 of the VGA connector (HS and VS) are digital signals, so can be driven directly from two FPGA pins.
Pins 1, 2 and 3 (R, G and B) are 75 ohm analog signals. With 3.3V IOs, use three 270 ohm series resistors. The resistors form voltage dividers with the 75 ohm resistors in the monitor inputs so that 3.3V become 3.3*75/(270+75)=0.72V, pretty close to 0.7V. Driving these 3 pins with different combinations of 0's and 1's gives us up to 8 colors.
Ground pins are pins 5, 6, 7, 8 and 10
multiplexed internals, and only internals data access. shared or no registers - how to specify such a design...
Visually:
1] That we can draw components and connect them within a schematic entry which ranges across low and high level (black-boxed) components both from a common library and generated from our own code (using the Create Schematic Symbol entry under Design Utilities in Process).
We can access such created components under the filepath in Categories in the schematic editor when we create say a new overarching design which specifies the connection of large-scale modules/components.
2] That we can (when we select new source) choose further modules from the IP (Coregen & Architecture Wizard) option - this are classified as to various categories, including DSP, math functions, memories, and basic elements such as counters and multiplexors.
3] At the same time using the View/Edit Placed Design (Floorplanner) (under Processes: Implement, Place and Route) we can see how the logic circuitry and I/O are assigned to the CLBs (configurable logic blocks).
From the Floorplanner toolbar we can toggle ratsnest (connection) display and zoom in and out.
Macro and micro views:
http://www.frank-buss.de/lispcpu/index.html
which defines in Verilog output (pins) RAM (on the FPGA), program counter, registers and very basic evaluator (which evaluates hard-coded instructions) - the output in this instance is to slowly flash one LED! This example demonstrates I/O pin assignment
further SDRAM:
http://www.xess.com/appnotes/an-071205-xsasdramcntl.html
Describes/implements/wraps up an SDRAM controller core.
audio:
In the instance of audio perhaps rather than dealing with the on-board audio codec of the XSTend borad, perhaps we should make use of raw 8 bit I/O from prototype area (to primitive soundcard or schmitt trigger box) - prototype area can be connected to adjacent J4 which accesses all the prototype pins from the XSA-50 header (we can look this up in the manual for assignment).
and video:
We can use VGA (some cores/sample projects - note that a useful experiment would be to send voltages (0->0.7v) for RGB signals raw to monitor... or we can use video out on XSTend board, or just resistor ladder from XSA-50 data pins as suggested in ntsc example on:
http://www.xess.com/ho03000.html
where we find all project examples.
Boards used:
XSA-50 development board (Xilinx XC2S50 FPGA (Spartan II/2), 128K Flash memory for FPGA bitstream, 8 Megabyte DRAM).
and XSTend board V3.0 (XST-3.0) from XESS
(stereo codec, dual channel analogue I/O, video decoder, ethernet, usb, rs-232, ide)
see:
http://stewks.ece.stevens-tech.edu/CpE487-S05/HomeworkF04/:/hlisiteB/NotesForXessBoard.html
... example code is in VHDL.
see also free_fpga_guide for some background and install of Xstools from XESS:
link: Xstools RPM: http://www1.cs.columbia.edu/~sedwards/software/xstools-4.0.3-1.i386.rpm
x____
stages:
0] Re-install WebPack (this version 8.2.02i) from Xilinx:
http://www.xilinx.com/webpack/
1) using web-based installer which is a very lengthy process.
2) then we use the opening lines from the shell script at:
http://panteltje.com/panteltje/fpga/index.html
(which outlines solely commandline use of Xilinx toolset.)
mkdir /usr/local/lib/xilinx/ cp ~/Xilinx/bin/lin/*.so /usr/local/lib/xilinx/ echo /usr/local/lib/xilinx >> /etc/ld.so.conf ldconfig and: export XILINX=/root/Xilinx
then we can run bin/lin/xst commandline program
for full GUI:
bin/lin/ise
1] connect parallel port. start laptop. power up XSA-50 board. launch xstest from commandline to test:
xstest -b xsa-50
launch WebPack (command: Xilinx/bin/lin/ise)
2] create new project (here we define the device and the design flow)
Over the above tutorial and past work there is now a new project wizard - we skip over behaviourals and ports:
we create leddec (LED decoder as per tutorial)
3] insert VHDL module (describe/enter (in) VHDL code)
Double click on leddec in sources and edit templated source code.
4] synthesize - highlight module filename .vhd
Click on Synthesize-XST in Processes. Successful
5] implement design process eg. place and route
Highlight and then select Implement Design in Processes
6] new source - implementation constraints (I/O pins assigned as below). then Create Timing Constraints, then port tag:
Select leddec in Sources, right click and select New source following the example names as leddec_ucf, associate this with leddec and then expand User Constraints item in processes to access Create Timing Constraints - once there (new window opened for constraints editor) we can select the Ports tab to access port name attributed in our VHDL and hopefully assign pins (location) as gathered from XESS manual.
In this instance unable to enter text into Location field...
Rather we must choose Assign Package Pins from User Constraints in Process and enter pins here - then these can be double-checked in the above editor.
7] rerun implement design
Successful!
8] generate bitstream - Generate Programming File
Successful!
9] use xsload to download over parallel port - .bit file (in our project file as defined:
xsload -b xsa-50 -fpga ~/piksel/fpgatests/leddec/leddec.bit Configure FPGA: Downloading leddec.bit:fst field: ignoring 9 bytes 100%
(strangely enough produces an error when run from eshell)
in the first example LED decoder from the above URL the xsport utility is used to send bit patterns to the parallel port:
eg:
xsport 101
b) understanding of RAM and I/O pin access with XTEND board - again using example code. also perhaps audio and simple video
I/O pin access (which is used within Implementation Constraints (ucf file)) is simply a matter of looking up pin assignments in the manual. The example above also gives some advice.
Design of LISP-Based processors ... or, LAMBDA The Ultimate Opcode
Guy Steele and Gerald Sussman (http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf ) 1979, MIT
To quote from the opening abstract:
We present a design for a class of computers whose 'instruction sets' are based on LISP. LISP, like traditional stored-program machine languages and unlike most high-level languages, conceptually stores programs and data in the same way and explicitly allows programs to be manipulated as data. LISP is therefore a suitable language around which to design a stored-program computer architecture. LISP differs from traditional machine languages in that the program/data storage is conceptually an unordered set of linked record structures of various sizes, rather than an ordered, indexable vector of integers or bit fields of fixed size. The record structures can be organised into trees or graphs. An instruction set can be designed for programs expressed as such trees. A processor can interpret these trees in a recursive fashion, and provide automatic storage management for the record structures.
further - an architecture and an instruction set are specified, fabrication of a VLSI prototype microprocessor is described.
1) LISP as a high-level machine language. Given that "LISP reflects the structure of program expressions in the structure of the data which represents the program." and also given that data and programs are equivalent and can equally be manipulated (within the "incestuous" realm of compilers and interpreters).
2) Tree structure rather than linear vector of instructions which can be indexed using counters and the like. Evaluation by recursive tree-walk.
3) Lisp atoms and lists are described in fine detail with examples prior to the exposition of a meta-circular LISP interpreter (ie. it is written in LISP and can interpret itself).
4) APPLY within this simple interpreter... in the case of primitive procedures:
"... primitive symbols are not to be confused with the atomic symbols used as their names. The actual procedure involved in the combination (car x) is not the atomic symbol CAR, but rather some bizarre object (the value of the atomic symbol CAR) which is meaningful only to PRIMOP-APPLY."
(thus further into the appendix the magic of execution is microcoded)
5) State machine implementation:
An interpreter in the form of a state machine controller. (rendering explicit as a control mechanism that which the recursive LISP interpreter hides - state information that must be saved on each recursive invocation).
Registers and a list memory system.
The evaluator in Lisp has five global registers which simulate the registers of a machine
EXP - hold expression or parts of under evaluation ENV - holds pointer to environment structure (context) VAL - value developed in evaluation of expressions ARGS - list of evaluated arguments CLINK - pointer to top of the list structure which is the control stack
Further LISP code such as EVAL-DISPATCH implements the simulation
6) Representing LISP data.
"Lists are normally represented by records each of which contains two pointers to other records. One pointer is the car and the other is the cdr."
(A (B C) D) becomes
_ _ _ _ _ _
|.|.+ -> |.|.+ -> |.|.+--> NIL
- - - - - -
| | |
v | v
A v D
_ _ _ _
|.|.+ -> |.|.+--> NIL
- - - -
| |
v v
B C
Pointer representation is unimportant. We give pointer to memory system and it returns the context of the record pointed to. A type field is associated with each pointer.
7) The state machine implementation is combined with typed pointer dispatch to form an interpreter which can be implemented in hardware (p. 15)
8) Storage management:
The system is divided into:
a) a storage system which "provides an operator for he creation of new data objects and also other operators (such as pointer traversal) on those objects."
b) EVAL (program interpreter) which "executes programs expressed as data structures within the storage system"
in classic Von Neumann style.
The storage manager here makes a "finite vector memory appear to the evaluation mechanism to be an infinite linked-record memory". Thus a garbage collector is implemented.
9) Physical layout of the prototype processor
"The evaluator and the storage manager are each implemented in the same way as an individual processor. Each processor has a state-machine controller and a set of registers. On each clock cycle the state-machine outputs control signals for the registers and also makes transitions to a new state."
...
"The contents any register is a pointer (8 bits in the prototype) and a type field (3 bits in the prototype). The registers of a processor are connected by a common bus (E bus in the evaluator, G bus in the storage manager)
....
"Each state-machine controller consists of a read-only memory (implemented as a PLA), two half registers (?) (clocked inverters, one at each input and one at each output), and some random logic (eg. for computing the next state)... two phase non-overlapping clock signals..."
1- registers are clocked. next state is computed
2- next-state signals appear and are latched
all signals from the controllers can be multiplexed onto twelve probe lines
10) Discussion
There is no ALU.
Possible addition of complex processors/devices on the external memory bus with LISP processor serving as controller.
At the same time talks of a layered approach wherein a line can be drawn at arbitrary points within a tower of abstraction = a boundary between evaluator and storage manager
"... a hierarchy of interpreters running in [a] virtual machine. Each layer implements a virtual machine within which the next processor up operates."
such a boundary also exhibits an arbitrary distinction between hardware and software. also the overlap:
"Each of the layers in this architecture has much the same organisation: it is divided into a controller ("state machine") and a data base ("registers"). There is a reason for this. Each layer implements a memory system and so has state; this state is contained in the data base (which may be simply a small set of references into the next memory system down (own note: no operation but only a mapping)). Each layer also accepts commands from the layer above it, and transforms them into commands for the layer below it; this is the task of the controller."
also in talking of analogies between common CPU and CPU here:
"We may loosely say that there are two addressing modes in this architecture, one being immediate data (as in a variable reference), and the other being a recursive evaluation. In the latter case, merely referring to an operands automatically calls for the execution of an entire routine to compute it!"
11) History of VLSI implementation
Typed pointers treated as instructions, with the types as "opcodes" to be dispatched on by a state machine...
Rough sketch of building blocks:
PLA library array cells, simple replicated register cells assembled using (LISP-based) software
12) Conclusion
A CPU "... organised purely around linked records, especially in that the instruction set is embedded in the organisation."
Finally concludes that just as the LISP tree data representation informs this particular instruction set and thus the CPU architecture (for it is not just a question of representation but also changing the means of manipulation), so other representations (for example graphs) or storage organisations could be examined.
13) Appendix - Prototype Lisp Processor Technical Specifications
For later examination.
so far... The Instruction Set:
The 3 byte type field supplies 8 "opcodes":
from 0=constant list to 7=quoted constant
Address part of the word has different purposes dependent on type.
Procedure call (type 6) is the most complicated of all:
"It is a list of indefinite length, chained together by CDR pointers
xx_____
Also of note here is the use of transistors and resistors (in this case depletion-mode transistors) which can be used to construct logic gates.
see also GC probe mux and multiplexor p61,62 - a grid of wires with transistor across for probes
register cell p 63
flip-flop:
flip-flop as (bistable, in the case of counters, registers and memory) multivibrator
http://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop01.html
inductor:
changing current in an inductor produces an EMF in the inductor which opposes the current change...
-> reactance (ohms) whuch is the ac equivalent of resistance and in case of inductor is effected by frequency (high frequency high reactance)
The Design of an M6800 LISP Interpreter, S Tucker Taft, BYTE August 1979
(notes for piksel, instruction sets as steps towards Lisp CPU or any kind of artistic CPU - an examination of hardware-based means of representation. At what point the necessary reduction (or why it is considered as such) into hardware makes sense. Or to keep all levels as a simultaneity. Comparison of high-level with instruction sets. At the same time some way - borrowing from the Lisp CPU - that we can eavesdrop in audio fashion on all internals of the CPU, not just registers a la self.c (own code see software) but also data paths. Indeed if such paths ans such an exposure are implied through a parallel switching architecture. The FPGA is attractive precisely as RECONFIGURABLE architecture or matrix rather than as RECONFIGURED.)
1) Underlying representation of lists using dotted pairs (two address cells). The left cell points to the first element of a list, and the right cell to the rest of the list. NIL is used to signify end of the chain. CONSing two atoms gives a dotted pair with CDR of final dotted pair as non-NIL atom.
(see also diagrams on:
http://www.gigamonkeys.com/book/they-called-it-lisp-for-a-reason-list-processing.html
)
2) READ, EVAL and PRINT loop
Internal representation of the list (the program) is called a form here - the form is evaluated according to the convention that the first element of such a list specifies a function, with the rest of the list as arguments.
3) Into implementation:
BIGLUP LDX PRMPAT get prompt atom
JSR PATOM print the atom
JSR READ read the form - result is in x reg
JSR EVAL eval the form - result is in x reg
JSR PRINT
BRA BIGLUP
PATOM is a subroutine, also used by PRINT when a form is tested as an atom.
M6800 index (X) register - 16 bits long use for all object representations/forms
Dotted pairs must hold two forms - thus 32 bits (4 consecutive memory bytes)
Internal representation for atoms:
For symbolic atoms two items of information are needed:
thus 4 bytes chosen with first 2 as memory address of print name and third of fourth holding value (form) of the atom
A way to distinguish dotted pairs from atoms is needed:
In this instance all dotted pairs and atoms are aligned on 4 byte boundaries which means that we can use the lowest two bits 00 01 to encode type and garbage collection (GC) information.
With numeric atoms name determines value and hence only name (or value) needs to be specified. Representation was chosen with high order bit set, 14 bits numeric value and 1 for GC (seeing as only 0000 through 7FFF is used for atoms and dotted pairs storage bit so when forms specify this high order bit is free.
Special representation for the NIL atom High order byte is zero (which rules out 256 byte page starting at zero).
x_______
A linked list (called OBLIST) of all defined symbolic atoms is used for example by READ and also the EQ function. READ checks prior to allocating 4 byte cell for atome of given print name. If found, returns form specifying the pre-existing atom. Otherwise, copies name into name storage area, allocates 4 byte cell, inits left cell to point to name and right to NIL and returns form.
x_____
READ function
Builds up internal representation - allocating dotted pairs and atoms. If expression is a list READ returns the first dotted pair.
RATOM does the work of allocating new cells as above. Deals with parentheses with recursive calls to READ.
(code p143)
PRINT function
Takes a single form as argument, and types the value as fully parenthesised LISP expression.
EVAL function
The heart of the matter.
EVAL accepts one form as argument and evaluates it according to the convention:
"the value of NIL is NIL, the value of a numeric atom is itself, the value of a symbolic atom is the form associated with the atom, and the value of a list is determined by applying the function specified by the CAR of the list to the list of arguments which make up the CDR of the list."
SUBRs and LAMBDAs: SUBRs as built in functions written in machine code (eg. CAR< CDR< PATOM). LAMBDAs are user defined.
The system here treats the bytes which make up the machine code of the SUBR as the print name of the atom. SUBR specified with dotted pair and car as atom SUBR. Machine code is also prefixed with a special string.
(p147 code listing)
in a GNU Emacs buffer:
M-x (Meta-x or Alt-x) iso-accents-mode
Then for the umlaut: " followed by letter, eg. "u
see:
http://www.gnu.org/software/emacs/manual/html_node/Minor-Modes.html
ffmpeg -i source.avi -target dvd -aspect 16:9 -sameq outfordvd.mpg
simple.
except. this doesn't seem to write correct headers for dvdauthor:
STAT: Processing five_dolls.mpg... WARN: System header found, but PCI/DSI information is not where expected (make sure your system header is 18 bytes!)
also:
http://www.emacswiki.org/cgi-bin/wiki/
http://homepage.mac.com/cariani/:/PaskPaper.html
http://www.armyofclerks.net/#dendrite
http://www.jefspalace.be/digital/game%20of%20life/index.htm
also:
http://www.stanford.edu/class/ee183/tao.shtml (for XESS board and Verilog)
no instruction set but collection of singular parallel instruction/data streams - switching between these (FPGA implementing a reconfiguration itself)
a new architecture
Very high speed integrated circuit Hardware Description Language.
description of behaviours (component for example an AND gate) as an entity/architecture pair are combined
links:
http://esd.cs.ucr.edu/labs/tutorial/
http://instruct1.cit.cornell.edu/Courses/ee475/
http://www.arl.wustl.edu/~jst/cse/260/dp/cpu.html
Easier to learn (closer to a programming language), offers variety levels of abstraction
links below:
or even:
Bill Seaman (http://digitalmedia.risd.edu/billseaman/pdf/tb_endoNeo-1.pdf )
Konrad Zuse (ftp://ftp.idsia.ch/pub/juergen/zuserechnenderraum.pdf )
Guy Steele and Gerald Sussman (http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf )
Building blocks of an FPGA
logic gates, lookup table, flip-flops (memory)
"The configurable logic blocks (CLBs) in the FPGA can be further decomposed into look-up tables (LUTs) that perform logic operations."
running in parallel. a question of clocks and frequency
further FPGA/CPU links:
http://members.optushome.com.au/jekent/Micro8/Micro8.html
(see Verilog as HDL: http://www.kuro5hin.org/story/2004/2/27/213254/152 )
some hints:
http://www.pjrc.com/tech/8051/ide/wesley.html
http://server.barrymichels.com/ide/
http://www.compuphase.com/mbr_fat.htm
http://www.eurosource.se/akhe/links.html (search down for hard drive)
with temporary graphite connections - test smaller self-switch board with circuit diagrams, on-board power and amps.
1] Notes regarding the Lisp CPU
(Steele and Sussman 1979)
2] Mix design of self-switching active circuits with FPGA/Instruction sets
with perhaps also addition of video sync signals and generation
// [ also use of 74x14 as pulse stretcher]
3 sets of 3 schmitt triggers in various configurations
2 sets of 3 logic gates
2 generic sets pots and diodes (and I/O)
1 set (for module attachment)
(but what about digital input from parallel port? - 48 points (1024 switches) = 12 circuits = 4 extra, one digital I/O, one op amps, one transistors, one capacitors to ground say)
so we need (for 1024) 128 shift registers and 256 4016/4066s
design as modular boards = 8 registers makes 16 boards with 16 4016s also on each
and some sort of modular connectivity
without question of meta-switching - switching itself of 1024 switch combinations from 48 points. unless both sets of points are exposed for manual connectivity but it would be nice to connect by way of software.
(or the possibility of a smaller say 64 switch (8 registers, 16 4066s) with all switches exposed and 128 crocodile points for switching other matrix box points)
1) VLF reciever using OP27
2) op-amp variations
3) LED-LDR circuit
4) 555 triggers
5) more logic (AND self-referred)
6) test for 74HC595 shift register based switch circuit
cumulative addition (for the site)
at the same time as some sort of indicated (perhaps by way of embedded lisp code using markup) version control
for a CPU:
(again)
http://www.async.ece.utah.edu/~myers/nobackup/ee3700_99/xilinx/lab8.html
(as looking into encryption/Turing and the vocoder)
So then we built a test rig consisting of a vacuum cleaner motor, some pulleys off a little trolley and that ran tape round and gave signals out from the photocells.
http://www.paia.com/vocodwrk.htm
mimes same design principles across layered vm segments
low level/high level
(Lisp typified as high-level machine language)
further simulations-machinery operates as parallel such micro-/macro-equivalnce CPUs
http://sci-toys.com/scitoys/scitoys/computers/radio/computer_controlled_transmitter.html
In relation to quotation:
We work at the commandline making use of small custom-coded applications. The application is entered and prompts for user input, where necessary, supplying further information and prompts - an interactive application (similar to REPL of a Lisp - a model behaviour). The editor (GNU Emacs) presents an extendible code-face environment whilst at the same time wrapping this with a system of questions and prompts (interrogative). At the same time we can run a Lisp (by way of SLIME also) within Emacs - we can evaluate expressions, define functions, execute code and connect to processes, yet within the prompt model and on the surface of an expression - a necessarily valid expression. In contrast coding our own REPL allows us to enter a new level of prompting where we can define the nature of our own expressions; for example, solely the nesting of brackets. We are within a closed environment.
1) 3 base transistor circuits
2) transistor board
3) caps, diode inhibitor and 7404 board
4) logic board
5) 4016 and 4066 switch board
6) 40106 with MAX3232-based transistor avalanche and 7404
7) transistor Schmitt trigger board
(todo thus: relays, op-amps (feedback) and series of 555 triggers)
for broccoli... (all pins on 18pin socket fine, but uses 5 parallel prot lines for communication whereas broccoli uses 4)
or modify noppp code:
clues from noppp_lx code:
// Uses two-wire serial data communication through printer port.
// Pin 1, STROBE, is serial clock;
// Pin 14, AUTOFD, is serial data out to PIC;
// Pin 11, BUSY, is serial data in from PIC;
// Pin 17, SLCTIN, is low when writing, high to provide pull-up when reading;
// Pin 2, D0, is lowered to apply Vpp.
// SLCTIN and BUSY are tied together for pull-up and for hardware detection.
// (In current versions this is done through diodes or gates.)
and....
// PIC MEMORY MAP
// The PIC16F84 has four programmable memory areas
// (plus data RAM, which is not programmable).
// Config memory is only 1 byte, but is treated like the others.
// Base address of each memory
#define PBASE 0 // Program memory
#define IBASE 0x2000 // ID memory
#define CBASE 0x2007 // Config memory
#define DBASE 0x2100 // Data Memory
#define PSIZEMAX 8192 // Max size of each memory
#define ISIZEMAX 4
#define CSIZEMAX 1
#define DSIZEMAX 256
1) The problem is that the PICs configuration bits are not being cleared and reprogrammed as thought.
./readcfg (after ./erasepic) always reads same data
It seems to erase we need to bring MCLR from GND to ViHH (12-14v)
(just connecting it to ViHH, well of 12v from 9v and 3v batteries in series, doesn't work.)
see:
http://web.interware.hu/lekovacs/PIC/index.html
and:
http://www4.tpg.com.au/users/talking/Burning%20a%20Chip_Page1.html
also length of parallel port cable may be an issue...
(also brocolli now doesn't work with main laptop t20)
1) readpic (which is used to read PROGRAM memory - EEPROM data memory is accessed by way of readdata) has options the wrong way round -
length is first and THEN address a la:
./readpic 512 0
(read first 512 bytes) - we see it matches monitor.hex
but are config bits set?
try 9v to Vpp/MCLR (pin 4) and erasepic - yes configuration bits erased
and with writepic they are programmed!
2) next step is to re-test serials...
http://www.seattlerobotics.org/encoder/mar97/basics.html
The basic function of a pull-up resistor is to insure that given no other input, a circuit assumes a default value. Actually, there are two flavors of this circuit. A pull-up and a pull-down. Their function is the same, to create a default value for a circuit, but one pulls the line high, the other pulls it low.
1) Monitor-running PIC is powered from regulated 5v supply with 10k resistor from Vcc to MCLR (pin 4) and 2.2 uF Tantalum across Vcc/GND connected via MAX3232 circuit to second laptops serial port
2) Second laptop is loaded with darcs (yum install darcs) and then brood. Running now brood -e purrr as before
2.5) (purrr sheepsint) restore
3) ping returns random stream of numbers or nothing
4) as per example for sheepsint:
( : click PORTB 3 toggle ; ) upload
either returns 7681 0012 FFFF FFFF
or:
7681 0012 7681 0012
And then the following: ( click ) trun
nada!
5) Troubleshooting:
a) PIC is badly programmed: verify using parallel port programming circuit!
b) hardware problem with PIC on breadboard (noise): make small veroboard circuit with socket and parts! test very basic code
c) or serial section: program PIC for standalone serial echoing say!
d) problem with serial port on laptop: ????
e) problem with cat/purrr: last step! revert to earlier pulls, test, debug
darcs get --partial http://zwizwa.goto10.org/darcs/brood
(setq planner-rss-base-url "http://1010.co.uk/") (setq planner-rss-category-feeds '(("." "~/Wiki/feed.rss" "<?xml version=\"1.0\" encoding=\"utf-8\"?><rss version=\"2.0\"><channel> <title>ap/xxxxx/1010</title> <link>http://1010.co.uk</link> <description>xxxxx projects</description> </channel></rss>\n"))) (setq planner-rss-feed-limits '(("." nil 10)))
now single escape \
XML Parsing Error: syntax error
(first gives - search failed - channel ??)
on the road:
http://www.ntu.edu.sg/home5/PG04878518/:.html
(now writes feed.rss with nada)
url-http.el is suspect but works fine for other URLs?
(now testing planner-rss.el for rdf production)
following:
http://zwizwa.goto10.org/darcs/brood/doc/purrr.txt
and:
http://zwizwa.goto10.org/darcs/brood/doc/sheepsint.txt
Using PIC18F1220 (18 pins) and simple parallel port programmer as per:
http://home.earthlink.net/~davesullins/software/pic18f.html
(but using 5v 7805 regulated supply instead of 3v and thus 330 Ohm resistor).
(the only other programmer found is more complex/safer Tait-style design:
http://web.interware.hu/lekovacs/PIC/index.html
)
and Broccoli18 software (v. 0.8pre1).
With enough battery power we can ./readcfg
which tests the parallel port connection:
Device id 07 e7 Found PIC18F1220.
and ./writepic
...
but first how to generate monitor.hex to communicate by way of the serial port with our PIC:
1) From ~/brood/bin we can run brood -e purrr
from within which (ie. after running we type in):
(purrr seed sheepsint) use
to create:
(in Tom's words):
... a monitor for the 18f1220 chip, running an 8Mhz oscillator (internal) and uses a 19200 baud serial link to the host pc.
which is saved in ~/.brood/purrr/sheepsint
where we also have state.cat and init.cat and state.cat (equivalent)
(see also:
http://zwizwa.goto10.org/darcs/brood/doc/new.txt )
2) Use Broccoli18/writepic we burn monitor.hex (from there) onto PIC
3) Now over to the serial MAX232/3232 connection with the PIC:
RS232 link to host PC and capacitors connected for MAX as per:
http://www.geocities.com/vsurducan/electro/PIC/pic84lcd.htm
....
(next stage working over serial port (lacking on the IBM T40 here))
but monitor should run as:
/brood -e purrr
and then dive in...
(add-to-list 'load-path "/~/delicious-el") (require 'delicious) (setq delicious-api-user "myusername" delicious-api-password "mypassword") (delicious-api-register-auth)to .emacs.
but aside form any consideration of the ACTUAL software
specifying this environment and providing configuration and additional command-line tools and extensions to avoid wasting time checking through a huge range of packages.
1) delicious integration
http://www.wjsullivan.net/delicious-el.html
to test...
2) bookmarks transfer from firefox to w3m
Use macro but may have to insert bookmark headers by hand or write a script
3) rss feeds and how subscription happens
see planner-rss.el
In a similar way, we can regard the evaluator as a very special machine that takes as input a description of a machine. Given this input, the evaluator configures itself to emulate the machine described. For example, if we feed our evaluator the definition of factorial, as shown in figure x, the evaluator will be able to compute factorials.
http://mitpress.mit.edu/sicp/full-text/sicp/book/node81.html
also:
In this chapter (five) we will describe processes in terms of the step-by-step operation of a traditional computer. Such a computer, or register machine, sequentially executes instructions that manipulate the contents of a fixed set of storage elements called registers. A typical register-machine instruction applies a primitive operation to the contents of some registers and assigns the result to another register. Our descriptions of processes executed by register machines will look very much like “machine-language” programs for traditional computers. However, instead of focusing on the machine language of any particular computer, we will examine several Lisp procedures and design a specific register machine to execute each procedure. Thus, we will approach our task from the perspective of a hardware architect rather than that of a machine-language computer programmer. In designing register machines, we will develop mechanisms for implementing important programming constructs such as recursion. We will also present a language for describing designs for register machines. In section 5.2 we will implement a Lisp program that uses these descriptions to simulate the machines we design.
to open hardware - data sheet exposes instruction set and opcodes (trusted computing in all senses) - or a form of reverse engineering (for reality CPU?) takes place by way of (aural) experiment. from the instruction set we can extrapolate an architecture
by way of SICP:
p492:
"To design a register machine (a traditional computer) we must design its data paths (registers and operations) and the controller that sequences these operations.
data paths as diagram
state machine as controller (?)
5.2 a Lisp program that uses such paired descriptiuons to simulate the machine
see also p384/5 (data as programs):
[fill in]
and p343+ - streams as signals (for further research on piksel/xxxxx overmapping - simulation of RC network and analogue system in relation also to time)
see Little Lisper p118+ (Friedman et al).
For our Salo language (which should employ some meta-level of quotes and brackets itself).
a continuous plane - or synchronous view of vertical (abstraction) hierarchy by way of overlap held:
1) FPGA (software)
2) Instruction sets - a transition or barrier for abstraction/ hidden
3) simulation (software)
isisu avi2isis ~/titel2.avi /mnt/isis-salo
Could not open avi movie file /root/titel2.avi
(and raw PCM sound? - is -aoc pcm substituted below)
The same, but with MJPEG compression:
mencoder dvd://2 -o titel2.avi -ovc lavc -lavcopts vcodec=mjpeg:mbd=1:vbitrate=1800 -oac copy
http://web.media.mit.edu/~stefan/isis/
(on Fedora Core 3 had to install from rpm of glut-devel:
http://rpm.livna.org/fedora/1/i386/RPMS.stable/
)
and then builds fine!
now onto Emacs integration....
previously:
An encoding of Salo according to some system or active scheme of representation.
encoding those enframings, insertions and contextual shifts (life as dream as life as dream) enacted by quotation.
a system of notation (software) mapping levels of action, quotation and description (Salo is such a case - in being filmed, in the act of filming a prescribed script - of expanded software). - relation and marking as itself also within Salo - systematics and enacted diagram overlap here is short circuit of the pseudo-scientific rationalism of de Sade and pornographic intent itself. Such a diagram/system of description can be extrapolated in the opposite direction as a system of creation.
also pragmatic notes - source code commentary
prescriptive formulas and recipes
How to produce such a mapping or system of notation - perhaps Lisp-based and making use of indentation and bracketting
and of course 'quotation within the language itself
linear time-line and nesting of action and notation itself
the language of Salo description becomes active language of fm01 creation
so here we have the idea of a paranthesis-led notation. a language which could be interpreted and such interpretation locked to the already noted frames and nested playback .
#204 4066 (quad bilateral switch) is pin compatible with 4016 17:05 (2006.08.09:4)
1) working with modified pf-rawvideo.mencoder script to jump to offset/seek in AVI for playback from PF script in PD. Can
successfully deliver param from PD to PF with:
: float >int dup accum ! ;
but when attempt:
: open dup movie ! # save movie filename accum @ pf-rawvideo 3 pack # build command line "r" open-program stream ! ; # open stream "( name -- )\tOpen movie file." doc
now all looks fine as pack makes list of program and arguments for open-program
but still errors out. also if we send the filename from PD, same problem. perhaps need to convert INT to string but filename from PD is string
2) along the way found out about Forth, pack, DS=data stack, RS=return
stack, and conversions such as >int
3) but returned to alice system-driven code and came up with:
(defun playbc (start frames) (system (concatenate 'string "mplayer -really-quiet ~/test.avi -ss " (format nil "~A" start) " -frames " (format nil "~A" frames) " -vo xv -slave -osdlevel 0")))
further PF, Packet Forth URLS:
1) Gentle introduction:
https://packets.goto10.org/wiki/
2) Base:
http://zwizwa.goto10.org/zwikizwaki.php?page=
3) Trickier:
"The virtual machine we had to our disposal was Pico [http://pico.vub.ac.be/], an educational language developed by Theo D'Hondt..."
Pico is a tiny but expressive programming language that was especially designed to teach advance computer science concepts to students in other sciences than computer science (such as Physics and Chemistry). In a sense, Pico can be seen as a non-trivial marriage between the power of languages like Scheme, and, the standard infix notation students are used to from ordinary calculus. A.o., Pico features garbage collected tables (i.e. arrays), higher order functions, objects, meta programming and reflection. But above all, Pico is small! Really small!
The Pico Metacircular Evaluator:
http://pico.vub.ac.be/mc/index.html
/usr/local/bin/pf-rawvideo.mencoder
/usr/local/bin/pf-rawvideo.mencoder
to pass numerical parameter (offset) from pf to (altered) /usr/local/bin/pf-rawvideo.mencoder (use -ss specify offset)
using stack operations and pack:
dup: duplicates top item on the stack
!: store in variable. eg. 513 MY-VAR !
pack: packs stack
but all methods complain of e_type: invalid argument type with ->100 (as param passed)
and if we hardcode filename in pf-raw... and pass stack with number then the same thing happens / or refuses to open file
/usr/local/lib/pf/script/time.pf
or segfaults when opening various AVI files
probably best to refer to PF (Packet Forth) and ffmpeg stuff anyways
(idea being to ditch AVI in Lisp in favour of Emacs/Lisp/SLIME/OSC to PD/PF linkage for SALO project)
OF uncompressed DV-video streams.
http://www.codecomments.com/archive274-2004-8-253120.html
lisp machine/cpu to clisp bytecode/virtual machine
http://clisp.cons.org/impnotes/intr-set.html
http://clisp.cons.org/impnotes/vm.html
crossing instruction set question with promiscuous (or in the words of Design of LISP-Based Processors... LAMBDA: The Ultimate Opcode, an "incestuous software" realm of software manipulating software as data: "program editors, compilers, interpreters, linking loaders, debugging systems...") coding - such as at core of the viral (extreme promiscuity) - the compiler (... Trusting Trust)).
virtual shared memory model on a VM.
The bytecode can be thought of as being interpreted by a virtual processor. The engine which interprets the bytecode (the implementation of the virtual machine) is actually a C function, but it could as well be a just-in-time compiler which translates a function's bytecode into hardware CPU instructions the first time said function is called.
The virtual machine is a stack machine with two stacks:
STACK - a stack for CLISP objects and frames (Lisp stack). SP - a stack for other data and pointers (Program stack).
Also Pico Lisp looks interesting from VM POV:
http://software-lab.de/ref.html
"First of all, Pico Lisp is a virtual machine architecture, and then a programming language."
"... the one-to-one relationship of language and virtual machine of an interpreted system"
from FAQ:
Would it make sense to build Pico Lisp in hardware?
At least it should be interesting. It would be a machine executing list (tree) structures instead of linear instruction sequences. "Instruction prefetch" would look down the CAR- and CDR-chains, and perhaps need only a single cache for both data and instructions.
Primitive functions like set, val, if and while, which are written in C now, would be implemented in microcode. Plus a few I/O functions for hardware access. EVAL itself would be a microcode subroutine.
Only a single heap and a single stack is needed. They grow towards each other, and cause garbage collection if they get too close. Heap compaction is trivial due to the single cell size.
There is no assembly-language. The lowest level (above the hardware and microcode levels) are s-expressions: The machine language is Lisp.
http://www.rdrop.com/~cary/html/computer_architecture.html#simple_cpu
interesting in mention of PIC-based interpreter
(design of modular PIC system for reconfigurable audio)
see also PICBIT:
http://w3.ift.ulaval.ca/~dadub100/files/picbit.pdf
mention of CADR Verilog code
solely referenced by start and end points catalogued as contra to fm01 mantra
yet such points can be entered into the alice.lisp style representation/querying system and film generated which matches certain queries or as a functional response to an investigation
Schemix:
Schemix is implemented entirely in kernel space. It implements an arbitrary number of Scheme interpreters, each one separate from the others, and each one attached to some device in the /dev hierarchy.
http://www.abstractnonsense.com/schemix/index.html
Movitz:
The Movitz system aspires to be an implementation of ANSI Common Lisp that targets the ubiquitous x86 PC architecture "on the metal". That is, running without any operating system or other form of software environment. Movitz is a development platform for operating system kernels, embedded, and single-purpose applications. There can potentially be several completely different
operating systems built using Movitz.
More developed: http://common-lisp.net/project/movitz/
check out CVS
Algorithmic movie editing in Lisp:
http://blogs.bl0rg.net/netzstaub/archives/000831.html
https://bl0rg.net/~manuel/schnitt.lisp
The two opposing approaches:
1) Low-level modification (patching) of an existent operating system (GNU Linux, Hurd, other candidates?) or creation of x86-based
promiscuOS (virtualised a la Xen or not).
2) High-level sandboxed shared user-space a la ap0202 but as a (user-) space within which software can be compiled or interpreted and executed on a virtual machine layer which implies (an
intentionality of) leakage
...
Understanding the Linux Kernel (O'Reilly, Bovet et al.):
p376+
... the Linux Page Fault exception handler must distinguish exceptions caused by programming errors from those caused by a reference to a page that legitimately belongs to the process address space but simply hasn't been allocated yet.
do_page_fault() function (where? - arch/i386/mm/fault.c) is interrupt service routine for the 80x86 arch...
(from Linux Kernel Primer, PTR, Rodriguez et al:)
p238+
hardware interrupt 14 occurs when processor identifies the following conditions/exceptions:
(note exceptions can be classified as faults: the EIP is the address of the instruction that caused the fault - hence allowing instruction to be resumed if the condition is corrected. and if not...)
and from p183+
we find that the page tables are provided by OS to the MMU (Memory Management Unit - note lacking in sat Motorola 68000 and thus uCLinux port) to enable translation between virtual and physical addresses and to allow paging. (thus phys=virtual under uCLinux) - hardware promiscuity is perhaps promoted by this lack of abstraction, this bare equivalence.
3 bit error code is pushed on the stack by control unit when exception occurred:
do_page_fault is charged with handling possible scenarios, first up reads linear address that caused page fault.
mm_struct descriptor is for process memory
bad_area
jump to label bad_area if (what we're interested in) task's memory region does not include the address or address is not in current task's address space
thence:
is it in user_mode -> SIGSEGV
no - then jump to no_context:
if there is not an entry in the exception table for the offending instruction, we end up with oops screen dump
thus:
for promiscuOS, sharing process memory could be achieved at the level of hardware (uCLinux inspired), process memory creation (allocation) or some kind of patch to the page_fault handler (??)
Creating a Process Adress (p392+ O'Reilly)
clone, fork, shared memory space, parent space, COW...
from promiscuOS::
All process memory is (un)intentionally readable and writable by any process or user.
1] Elementary electronics p123
The bistable multivibrator. Four of these (the last three lacking a fourth transistor (NPN)) are linked on p166 to construct a binary counter which counts input pulses.
2] How does a CPU detect a memory violation?
Simple question. How it knows of memory boundaries and/of running process for SEGFAULT signal (11?) and how could succesfully override?
3] Possible Lisp-coded AVI manipulations of SALO
(of life_coding layers of quotation) for Riga presentation.
see Victor's 4-bit processor:
... the heart of the processor: a microcode instruction sequencer. This circuit turns instruction codewords into control signals that activate other processor components which in turn perform operations.
and this sequencer:
http://www.vttoth.com/vicproc_seq.htm
Perhaps the most interesting question with any processor is this: how do instruction codes (i.e., code words in memory) get turned into electrical signals that in turn trigger various events in the processor, altering its internal state?
as for address decoding this can be done a la ap0201 making use of 74LS573 latch which latches top 8 bits of (15 bit) address and then we can deliver bottom 7 bits straight from the PIC processor. then tell it to read or write to that address (within 32K NVRAM) - program and/or data memory.
CPU organisation notes::
so far we can read and write opcodes/data to/from memory
this is the work of the control unit which opens and closes gates to effect the circuits of execution
(to/from memory:
http://www.cellmatrix.com/entryway/products/applications/smallMemory.html
)
1. Fetch the instruction into an internal instruction register 2. Decode the instruction 3. Select (calculate) the operands (registers) used by the instruction 4. Fetch the operands from memory (CISC only) 5. Execute the instruction 6. Store (write) the result back in the proper place.
1) registers: (immediate storage), accumulator (or define registers such as memory address, memory data, instruction register
D Flip-flop or D Latches
from Wikipedia ( http://en.wikipedia.org/wiki/User:B_rip )::::
The register operations of a digital system are defined by:
¢ The set of registers in the system
¢ The microoperations that are performed on the data stored in the registers
¢ The control that üorchestratesý the sequence of operations in the system
and:
Just as assembly language reflects the architecture of the individual microprocessor, the registers and the elementary operations performed on the data stored in the registers (called microoperations) are described using a üsymbolic notationý referred to as a Register Transfer Language (RTL).
A Hardware Description Languages (HDL), like Verilog, also allows us to describe these microoperations. When taken in the context of an HDL behavioral description, these microoperations are collectively known as the Register Transfer Level (RTL). To avoid confusion, for this class, RTL will always be defined as üRegister Transfer Languageý and alternative terminology (i.e., Dataflow and Behavioral) will be used when describing a Verilog description of a microoperation.
D ð A + B
In this simple example, RTL notation is used to show the contents of registers A and B acted upon by the addition operator with the result placed into register D.
register file and ALU is known as data path.
2) control unit: microcode sequencer (pulses of microcode/data to ALU) - control gates decode the instruction sending signals to ALU or memory - circuits are reconfigured
microprogram - stored sequences in control memory - further abstraction
or hardwired
3) ALU (as below) - combinatorial logic is used - encoded by x bits to effect required arithmetic operation
MUXes and decoders and gates
4) address decoding and memory
5) program counter - binary counter
how implemented on CPU?
fetch instruction (from memory address - question of addressing), decode , fetch result, increment program counter
and on an FPGA?
question also of how address decoding functions
1) 240 gate as oscillator with electrolytic (10uF) to GND and 1M VR across gate. feeds into array of 74hc14 with inputs to gate pulled by VRs (1M) to GND and entry to next gate across 0.22uF capacitor. experimented with various diode, LED and feedback (across both sets of gates) techniques (and result fed through
another 240 gate without VR) but not so satisfying results
as per:
http://library.solarbotics.net/circuits/misc_sound_tgray.html
also resistor/DAC ladder
1) tie fence (if it is conductor) to one arm of potentiometer on 40106
circuit constructed
2) chain of floating 74x240s (using all 8). 2 buffer/invretors feed via 0.22 uF (marked 224) into each other and with an LED across the 2nd buffer/invertor and a 1M variable resistor connecting 2 inputs (or only across 2nd as with LED). interesting oscillations... also
pins 1 and 19 tied to gnd to enable the invertors.
range of possible connections.
3) Schmitt trigger from Beam article: positive/negative feedback
negative feedback - 74x240 invertor with resistor across input to output - towards balance point is half Vcc - 240 transmits high frequency waves (see CMOS radio transmitter)
positive - adds to input and steers away from 1/2 Vcc balance zone
240 has single threshold - 14 has two (positive and negative going as per hysteresis)
using negative feedback (resistor from output to input and say 1M input resistor) we can alter hysteresis thresholds
(if it was non-inverting like a 245 we could create + feedback or with 2x 240 in series and with resistor across both)
for example:
http://www.cellmatrix.com/entryway/products/applications/8bitALU.html
and:
http://www.cs.trinity.edu/About/The_Courses/cs301/04.computer.circuits/04.comp.cir.html
is interesting as it uses Scheme to model the ALU/logic
http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/20-relays/zuseadd.html
(but need to find more schematics)
http://web.cecs.pdx.edu/~harry/Relay/Overview.txt
http://hjs.geol.uib.no/zuse/zusez1z3.htm
Calculating Space. Rechnender Raum. Zuse - cellular automata
cellular automata and fpga as possibility. language.
http://germanium.cs.wustl.edu/ToyCPU/toy_cpu.html
http://www.holmea.demon.co.uk/Mk2/Schematics.htm
http://www.zetetics.com/bj/papers/piscedu2.htm
http://cis.k.hosei.ac.jp/~yamin/lectures/organization/single-cycle.html
http://www.iit.edu/~kottven/project2.htm
http://www.pjrc.com/tech/osu8/sch/osu8.html
http://www.physics.mcmaster.ca/phy4d6/Lab/chapter6.htm
http://en.wikipedia.org/wiki/User:B_rip
http://www.vttoth.com/vicproc_block.htm
and an old reminder:
http://aggregate.org/:/TARIQ_SLIDES/paper.html
http://www.cs.umbc.edu/~squire/cs313_lect.html
either commandline a la jekyll
or worked into cur/whatever
simply samples time-frame window (say x microseconds, y bytes) and reverses this in the stream
[xyxy]->[yxyx] for 4 bytes - and carries on with next 4 byte window
5v
| cathode
---
/ \ anode
in---|------------------>
|
---
/ \
---
|
GND
day three theory
with common to emitter tying 1->2 of another 40106 gate
such transistor boards inc. potentiometer and resistor as for PCBs expanding box
list of expansion modules/PCBs::
(question of shared power sources)
1) 40106s as above 2) transistor board [built] 3) 4016/4066-based switches 4) relay-based switches 5) avalanche transistor 6) simple op-amp units or darlington pair amp / or 244 amplification 7) logic: 4070= 2 input EXCLUSIVE-OR; 4093= NAND Schmitt trigger; 4030= quad EXCLUSIVE-OR; also 4093 quad NAND as gated oscillator ->- feedback with VR and capacitor to GND 8) transistor-based Schmitt triggers 9) 555-based triggers/astable/monostable 10) resistor ladders/voltage dividers all resistors to DAC point, chain of resistors with accessible points AND? also maybe 4051 8 to 1 analog mux
see http://www.k3pgp.org/Notebook/Cmosdata/cmos4000.htm
experiment with 74LS04, 74x244 buffer as multiplex?, RC oscillator
74x244: is octal buffer/line driver with Tri-state output (tie 1 and 19 to GND to enable or use as control)
can be used as an amplifier
RC oscillator:
Electronic oscillators are often designed around an LC tank circuit, a tuned circuit formed with an inductor and a capacitor. But use of an inductor is not a requirement. Instead, the tuned circuit can be built using just resistors and capacitors. Such an oscillator is referred to as an RC oscillator.
(wikipedia)
First circuit working fine:
one old NPN transistor: SS106E
with 3 0.1 uF ceramics, two VRs and 47uF electro + 47k resistor and 1.8 K
collector back by way of 47 k to base and beginning of 3 caps (connected with 1.8 Ks to GND), also by way of VR to +9v. emitter to gnd. spkr with 47K electro across collector and GND (reverse polarity on last 40106 circuit so is NEG towards speaker).
How a transistor works:
NPN:
n type semiconductor (negative electrons) from the positive electrode (collector) to negative electrode (emitter). p-type region (positive holes) called base which stops current passing from collector to emitter - but if base is made positive enough (0.7v) in comparison to emitter the NP junction passes current. electrons injected from emitter never reach base, rather collector.
summarised from: http://www.du.edu/~etuttle/electron/elect2.htm
single transistor invertor:
(from: http://www.kpsec.freeuk.com/trancirc.htm )
note - need to add say 10k resistor to base inputs of transistors on PCB boards (also on fence radio circuit)
see: http://www.williamson-labs.com/480_xtor.htm
report:
1) avalanche transistor noise:
success with 2n3904s (NPN) as per:
http://willware.net:8080/hw-rng.html
but should do more with either extra 2n3904 as amp...
see: http://willware.net:8080/hw-rng.html
or using 74LS04 (biased by 2.7k resistor across I/O to bias into "linear region" where they act as op-amps)
white noise: very quiet
2) modified simple 40106 (Hex inverting Schmitt trigger) acting as
osciillator:
a) standard configuration is
-VR-R--¬ | | | |\ | -1-| >-|-2-> next stage | |/ | CAP | GND
Frequency dependent on R and VR and capacitor (higher uF, lower freq)
b) first step is inserting feedback transistor-based VR between 1 and 2
c) also VR between inputs of successive gates 3 to 1
d) untying capacitors to ground and put LED in transistor circuit
e) connect one of capacitor ends to wire ariel - radio and electromagnetic sensitivity - this will be fence/radio/street performance module:
outline all modules to be made with PCBs
f) used Darlington pair to amplify signal for small speaker
test oggs:
http://plot.bek.no/~crash2005/010806_40106.ogg
http://plot.bek.no/~crash2005/010806_40106_untied.ogg
research ideas:
1) input to 40106 circuit and how we can further effect from outside.
2) place 40106 gates in a loop
3) amplify transitor noise from avalanche
This device contains six independent gates each of which. performs the logic INVERT function.
as:
astable or monostable multivibrators
to add further layer of switching/automation/self-immersion for new synthesiser
also as add-on modules for old neural
circuit page 38 polytronic (DDR electronics kit)
voltage control on base, emitter to ground and resistance flows across positive (of controlled signal) to collector
program as described previously
1] 555 as astable circuit producing automatic series of pulses a la: http://www.doctronics.co.uk/555.htm#astable - timing portion consisting of 2 resistors and 1 ca[ (4.7 uF) (one VR light dependent, one 680 ohms determining frequency and high and low times of each pulse) 2] 555 also as accepting control voltage for frequency - pin 5 3] 555 as monostable trigger 4] Schmitt trigger - 2 transistors as in Polytronic book (2nd variation with both emitters tied and potentiometer to ground. addition of a 3rd transistor in place of one potentiometer new ideas/work/TODO: 1] today maybe tackle RC oscillator (p162 poly) and tone generator (p104) and compare circuits to basic electronics 2] make simple low-frequency radio circuit for connection to fences, street furniture (along with regular transmitter) (see above) 3] print all necessary data sheets (DONE) 4] plus all circuit modules outlined. 5] hysteresis in Schmitt triggers as gap between positive and negative going switching voltage hysteresis: a retardation of the effect when the forces acting upon a body are changed (as if from viscosity or internal friction); esp: a lagging in the values of resulting magnetization in a magnetic material (as iron) due to a changing magnetizing force. see: http://www.lassp.cornell.edu/sethna/hysteresis/WhatIsHysteresis.html and also noise in hysteresis in relation to avalanching: http://www.lassp.cornell.edu/sethna/hysteresis/noise.html and, http://www.lassp.cornell.edu/sethna/hysteresis/hysteresis.html
but w3m bookmarking - using a and v keys for add and recall (very basic)
is not integrated with usual Emacs bookmarks which now work with planner after we load planner-bookmark.el
from tech_notes ::
C-x r m - make
C-x r b - retrieve
C-x r l - list bookmarks
annotate from this list using e - edit annotation
also bookmark-insert - insert full text of bookmark
and their integration with planner:
C-x r m after all done opens up a remember buffer with bookmark URL
( I to view image)
but integrates by way or URL as below
TODO:
1) shift from firefox to w3m (how to export bookmarks?) and learn new
functionalities
2) make more use of local bookmarking and planner as notation system
(so untie from site updating)
is M-x remember from w3m buffer (whatever we are browsing) to fill in link automatically as below:
but need to research further on Emacs bookmarks, w3m and planner integration - some stuff below already on tech_notes page
[copied from research but should cover soon... ]
1) build simple programmer 2) build and burn bootloader 3) build serial interface [ see : http://www.geocities.com/vsurducan/electro/PIC/pic84lcd.htm ] 4) communicate by way of cat
[seems to be working though needs a heatsink on the 7805-based PSU - simple tests loading code from EPROM run].
next question is how to input code and save this!
2] electronics - use of 74LS244/245 as current amplifiers
74*04 or 74*240 as plain old invertor
others of interest include 74LS244, 374 buffers
further circuits:
a) relay-driven AND, OR GATES on boards (for piksel artefacts)
b) see also transsitor ODER-Schaltung and UND-Schaltung
c) capacitor and coil as oscillators
x- x-
3] also lisp interpreter for z80 research
brief search refs:
http://www.mcjones.org/dustydecks/archives/2005/06/08/41/
http://community.computerhistory.org/scc/projects/LISP/
http://www.informatimago.com/develop/lisp/lisp15-0.0.tar.gz
further ideas:
code as artefact also
lisp-processor (cells) in FPGA:
more on this on research and particularly xxxxx_at_piksel
https://www.gelato.unsw.edu.au/archives/comp-arch/2006-May/000903.html
MyHDL - Python HDL for generation of Verilog: http://myhdl.jandecaluwe.com/doku.php/cookbook:ff
CADR machine: http://home.comcast.net/~prunesquallor/memo528.htm
all to be documented here (particularly PIC 18F programming and PF work)
1) basic transistor circuits (to be completed)
2) RC oscillator
3) simple FM transmit and recieve
4) neural network (74HC14 and 40106) circuits
5) darlington pair
6) op-amps and feedback
7) NOT gate and other logic circuits
8) 555, square wave and further (transistor-based) Schmitt triggers
9) diode/transistor avalanche
10) PIC programming (Broccoli18 see
http://home.earthlink.net/~davesullins/software/pic18f.html )
http://zwizwa.goto10.org/darcs/brood/doc/purrr.txt
11) switch (4016/66) module
12) prototype 74HC595 -> 4016/66 swithces for self-switching circuits
13) using the 4051?
references:
http://library.solarbotics.net/pieces/parts_elect_ic.html
(see the 1381s: these "gate" a source until the voltage is above some "trip" limit, at which point it is allowed onto a third pin. These chips are discriminated by the voltage at which the 1381 triggers, with a single-digit suffix (a.k.a., its "rank") on the part number corresponding to the trip voltage:) there
http://www.cgs.synth.net/modules/cgs28_seq_switch.html
http://www.fairchildsemi.com/pf/CD/CD4051BC.html
http://www.williamson-labs.com/480_xtor.htm
http://boardroom.solarbotics.net/beamod/sonic.html
http://www.solarbotics.net/bftgu/tutorials_schmitt.html
http://www.doctronics.co.uk/4015.htm
http://www.doctronics.co.uk/555.htm
http://www.doctronics.co.uk/4016.htm
http://www.cgs.synth.net/modules/cgs21_super_psycho.html
http://www.uoguelph.ca/~antoon/gadgets/741/741.html
http://www.kpsec.freeuk.com/trancirc.htm
http://www.edn.com/index.asp?layout=article&articleid=CA313057
http://www.geocities.com/vsurducan/electro/PIC/pic84lcd.htm
http://www.cryogenius.com/hardware/rng/
also unrelated but deals with 74LS13:
http://www.docm.mmu.ac.uk/STAFF/A.Wiseman/Acorn/:/BB_87/BBC49.txt
it latches:
The 8816 basically consists of the FET array, supported by an internal 7-to-128 decoder and a latch corresponding to each switch. If you want to turn on a switch, just write the address and a set on/off bit, and voila: an X line gets connected to a Y line and stays that way until you turn it off or reset the whole thing.
(from http://microship.com/bike/behemoth/bikelab/910221.html )
http://products.zarlink.com/product_profiles/MT8816.htm
8 circuits with 4 points
grid of 32x32
and then need some way to re-address itself (decode own voltages as address for grid)
or 32x32 switches in grid formation (4016 x x) with similar comp-controlled grid mapping circuit points onto the switch inputs
(or these are done manually or some other means as otherwise is like switching 32 points to potential x)
need some way of buffering parallel port so is not overloaded/sinking too much current
4016:
When E is LOW, the switch is open.
When E is HIGH, the switch is closed.
so we need either to send data repeatedly for configuration or lapse and just set/unset individual switches from parallel port
(need to get the 74HC595 possibly from SEGOR in Berlin: Kaiserin-Augustin-Alle 14, Charlottenburg)
Further project is to start off with using
4016 circuit boards as switching additions to older schmitt box (possibly with amplifiers - generic amp boards)
schmitt trigger box. self-configurable circuit:
google for:
4051 synthesizer routing cmos
brings up a few sites of interest:
http://www.cgs.synth.net/modules/cgs28_seq_switch.html
and:
(search on page for 4051)
also for analogue matrix chip:
http://personalpages.manchester.ac.uk/staff/p.dudek/projects/scamp/
http://www.cgs.synth.net/modules/cgs51_wrs.html
and
http://www.cgs.synth.net/modules/cgs55_asm.html
see s3switch
and on Fedora Core 3 (2.6.9 kernel):
1) had problems with transcode - missing codecs, reinstalled from
source after installing libdv, libmpeg2, libdvdread, and lame
2) now using ffmpeg for DV:
ffmpeg -i ~/test1.avi -s 720x576 -r 25 -ar 48000 -ac 2 ~/test1.dv
plays fine with playdv
3) there is no /dev/video1394 directory so we must do:
# create the 1394 devices mknod /dev/raw1394 c 171 0 chmod a+rw /dev/raw1394 mkdir /dev/video1394 mknod /dev/video1394/0 c 171 16 mknod /dev/video1394/1 c 171 17 mknod /dev/video1394/2 c 171 18 mknod /dev/video1394/3 c 171 19 chmod a+rw /dev/video1394/0 chmod a+rw /dev/video1394/1 chmod a+rw /dev/video1394/2 chmod a+rw /dev/video1394/3 # install the modules modprobe raw1394 modprobe video1394
as a shell script
(thanks to:
http://www.ptgrey.com/support/kb/index.asp?a=4&q=184&ST=)
4) dvconnect as follows:
dvconnect -sv test1.dv
still nothing though....
1] three basic transistor circuits or configurations.
from our 25 Schaltungen... book:
1) emitter-grundschaltung 2) Kollektor-grundschaltung 3) Basis-grundschaltung
translated as:
TRANSISTOR CONFIGURATIONS
A transistor may be connected in any one of three basic configurations (fig. 2-16): common emitter (CE), common base (CB), and common collector (CC). The term common is used to denote the element that is common to both input and output circuits. Because the common element is often grounded, these configurations are frequently referred to as grounded emitter, grounded base, and grounded collector.
from:
http://www.tpub.com/neets/book7/25f.htm
which further explains these configurations
2] the digital as a hiding or obscuring process in some ways; a falsehood of software further reinforced by a faked exposure: "these ones and zeroes are physical voltages."
3] what is unity voltage gain?
A gain of factor 1 or (equivalent to 0 dB) where both input and output are at the same voltage level is also known as unity gain.
also see:
http://web.telia.com/~u85920178/begin/opamp00.htm
THE SIMPLE EMITTER-FOLLOWER. The simplest discrete circuit-block is the emitter-follower. It acts as a unity-voltage-gain buffer. A buffer is a stage with high input impedance and low output impedance; typically it prevents things downstream from loading things upstream. The simple emitter-follower does not have a gain of exactly one, but it is usually pretty close; this will depend somewhat on the output loading; don't expect the output impedance to be as low as a opamp with plenty of NFB. This page deals only with simple emitter-followers, ie those with one transistor as the actual follower. This count of one does not include extra transistors used as current-sources, etc to improve current-sinking behaviour.
http://www.dself.dsl.pipex.com/ampins/discrete/ef.htm
4] time and the C-R network:
arrival end of essay at the digital.
monostable vibrator
p63 (Penrose - PC interfacing) - monostable with one 555 chip
= 74HC14 quotation from data sheet:
The SN54LS/74LS13 and SN54LS/74LS14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have greater noise margin than conventional inverters.
Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input thresholds (typically 800 mV) is determined internally by resistor ratios and is essentially insensitive to temperature and supply voltage variations.
http://anarchy.translocal.jp/radio/micro/howtosimplestTX.html
http://tacashi.tripod.com/elctrncs/smplfmtr/smplfmtr.htm
http://www.scitoys.com/scitoys/scitoys/radio/am_transmitter.html
receivers:
diode between earth and antenna. we listen across the diode:
http://electronics.howstuffworks.com/radio9.htm
also
http://sci-toys.com/scitoys/scitoys/radio/homemade_radio.html
(all radio stuff here is very good but have lost link to other similar home-made caps one)
The Cardboard Variable Capacitor: http://www.crystalradio.net/beginners3/cap.shtml
http://www.mattknox.com/littlelisps.html
and (from incorrect link on that page):
PIC Scheme:
www.iro.umontreal.ca/~feeley/papers/sw03.pdf
Looking for a Z80 Lisp (Bit?):
http://www.iro.umontreal.ca/~dube/
Thanks to:
http://www.semis.demon.co.uk/PCB/PCB.html
see also http://pickledfeet.com/electro_noise.html
0) Make board tracks using transfers (from SENO in Germany, bought from Conrad) and an Edding 780 black marker 1) Heat up boiling water 2) Mix one 250g pack of Eisen III Cloride granules (Ferric Chloride III) again from Conrad in 1 Litre water in a glass jar (ADD granules to the water) 3) Pour boiling water into a small bucket 4) Place jar of Eisen solution in the bucket 5) While waiting to heat up drill 1mm holes in boards and tie with a metre or so of thread 6) Drop in boards so that they stand upright. Keep solution swishing back and forth 7) Check every five minutes by pulling out boards. Etching should take around 15 minutes. 8) Dunk boards in cold water and rinse a few times 9) Scour boards with washing up pads (damp) to remove black stuff 10) Drill and solder up
for a neural-network based synthesiser (a la older one with pins and crocodile clips) but totally reconfigurable by way of software - we have say 0-127 7 bits on parallel port which can set two 8x8 grids of connections within circuitry (8 circuits) - the second grid mapping voltages at points within the 8 circuits to the actual switching action of itself (what if can't sink so much current?).
we need to multiplex the parallel port 7 bits to 128 and latch these for the 4016 switches (4 switches in each) = 32 of these
we could imagine using 74LS373 Octal D-type transparent latches for latching (16 of these)
but to multiplex - 4 line to 16 line (74LS154) - two of these in grid connected in some AND gate configuration with latches.
questions:
1) how this could be simplified?
we need 8 latches
we're trying to decode 7 bit data representing one of 128 possible switches
address decoder?
see:
http://www.cgs.synth.net/other/paraport/paraport.html
74LS138 latches (3 to 8)
or even more simply::
http://computerchristmas.com/?link=how_to&:=25
following:
The design is based on 74HC595 shift register chips. The data is sent out serially one bit at a time and shifted through the chips. Each chip has 8 outputs, which drive 8 SSR's or Mosfets etc.
In the case of a 64-port system 64 bits of data are shifted out one at a time for each update. A latching pulse then latches the new data into all chips.
or PIC16F877 plus four 74LS154 plus latches
2) whether we can achieve same functionality in FPGA?
3) whether we should interface to PIC18F and start using purrr?
update:
could probably trim down to 8 circuits each with 4 entry/exit points (all connected to 1 entry and 2 exit) = 32 switch points and then we want the 32 to be able to switch also (itself switchable so another 32)
clarify:
first switch matrix: 32 (8x4 circuit connections) second switch matrix: those 32 switched by (digitally selected 8x4 voltages) third switch matrix: those last 32 switching the selection of points
total 96 with 64 from parallel port (with shift register can probably do away with latch and just keep updating very fast)
circuits: 1->4 Nv and Nu based as before 5 series of cmos invertors 6 series of avalanched transistors feeding each other 7 suspended bicore 8 NAND Schmitt (4093) or 1382 (CMOS triggers) or further logic based (NAND, AND, NOR)
Instead of bothering with tiny wires, Brattain attached a single strip of gold foil over the point of a plastic triangle. With a razor blade, he sliced through the gold right at the tip of the triangle. Voila: two gold contacts just a hair-width apart.
The whole triangle was then held over a crystal of germanium on a spring, so that the contacts lightly touched the surface. The germanium itself sat on a metal plate attached to a voltage source. This contraption was the very first semiconductor amplifier, because when a bit of current came through one of the gold contacts, another even stronger current came out the other contact.
from:
http://www.pbs.org/transistor/science/events/pointctrans.html
http://www.domenech.org/homebrew-sdr/receiver-1.htm
http://www.domenech.org/bt878a-adc/index-decimator-e.htm
transistor avalanche mode noise
(also:
http://www.freepatentsonline.com/5728963.html
and from elsewhere:
Just bias it with its base-emitter junction reverse-biased with a resistor in series to limit the current and a supply of about 9V or more. The junction will have avalanche breakdown at about 7V like a zener diode
also in general for transistors see:
http://www.du.edu/~etuttle/electron/elect2.htm
)
and:
http://willware.net:8080/hw-rng.html
(which also mentions /dev/random and entropy sources - see above)
"This circuit uses avalanche noise in a reverse-biased PN junction, the emitter-base junction of the first transistor. The second transistor amplifies it. The first two ALS04 inverters are biased into a linear region where they act like op amps, and they amplify it further. The third inverter amplifies it some more..."
also includes some nice notes/links for PCB fabrication
One of the best howtos can be found at:
http://www.tldp.org/linuxfocus/English/May2002/article236.shtml
(for Edding 780 use to hand-make boards)
see also:
http://www.xs4all.nl/~odu/pcb.html
http://www.fullnet.com/u/tomg/gooteepc.htm#1
http://www.freewebs.com/electronica/PCB/PCB%203/PCB%203.htm (seems ok)
also allied to this is high-res/frequency sampling a la
http://www.domenech.org/bt878a-adc/index-e.htm
by way of Klossowski's outline: Outline of Sade's system in Sade My Neighbour
is a mozilla based web browser designed to be completely keyboard driven, no compromises. It also strives to behave as much like Emacs as possible. This means all the keybindings and to-die-for features of Emacs that can be imitated by a javascript/XUL web browser Just Work.
also one could imagine a simple data addition and retrieval front-end once we have designed relations such as before/after, timelining, assymmetry of a pair, mirroring and so on as indicated below and in xxxxx paper:
link ripper and lewis carroll holographic coding of such rabbit holes ripper knowledge base as lisp lists after Norvig - check out: time machine time after time alice in wonderland (film) p146 - pkd mother goose how this is mapped out - embedded frames and environments frame languages mapped by relation - major categories - ripper, alice, pink light, trajectory, entropy ripper->entropy de_quincey->entropy and of embedding prolog kind of terms - to-left-of, is-mother-of levels of relational syntax (ripper lefthanded) what is lefthanded (lefthanded left assymetry) (mirror asymmetry) (alice mirror looking glass) (alice author lewis carroll) (carroll dodgson assumed ripper) or inferred (ripper alice) **knowledge base a la NORVIG: 1) possible poetic relations in new prolog type language timeline in prolog relation. later before. but then would need assymetry operator (backwards, forwards) 2) and also attachment of text chunks 3) possible worlds [ 496+ MRS system, 1985 Stuart Russell see krep.lisp which has frames and worlds - relations etc. knowledge representation fm01/fm01lisp/norvig -> prolog.lisp and prolog.dat (examples): (nature-of-relation '(pink-light alice ripper)) (pink-light [nature] scenes "exterior orbitting computation") -- embeds mother goose embeds alice (p146 quote) (alice looking glass) (relation nature related)
One then uses the system by:
quoted from:
http://www.cse.unsw.edu.au/~billw/cs9414/notes/prolog/intro.html
eval
code passed by way of the panel.lisp message board
or time-slice and code walking as a better option (see erunticlab modified creatures to become characters)
http://lucy.media.mit.edu/~mueller/storyund/storyres.html
Frame Activated Inferences in a Story Understanding Program
http://www.norvig.com/ijcai83.html
M-x find-name-dired
M-x find-grep-dired
http://www.gnu.org/software/emacs/manual/html_node/Dired-and-Find.html
but how to grep dired buffer?
a) mark all files in dired buffer (t key to toggle marks)
b) search with A key. M- finds next match
buffers, FIFOs - difference? copy opertions across FIFOs
also tie in to JACK leakage and containers
with reference to Distel but we don't really want to dig into Erlang...
looking at http://fresh.homeunix.net/~luke/shbuf/ which allows for shared Emacs buffers on top of Distel....
client.server application with serveur written in Erlang
also Termite on Gambit Scheme
or even simpler is Paul Graham continuation-led code in lisproc.lisp to be investigated [attempt for panel module to wrap up with querying, speech and OSC/PD macro]
C-f C-b character forward/back
M-f M-b word forward/back
C-p C-n lines
C-v M-v page
http://1010.co.uk/data_radio_v2.tar.gz
usage:
cat ~/xxxxx/alice/alice_1 | ./encoder and on receiving end radio input into linein soundcard: ./decoder
http://bc.tech.coop/blog/060515.html
also for panel module thinking on where is old lisp processes code which makes use of continuations from Paul Graham On Lisp:
~/fm01/lisproc.lisp
some success in data transmission at 43200 samplerate, 8 bit, mono /dev/dsp3 access, 2400 baud using Linex USB transmitter.
first transmission of alice (volume on alsamixer low at white level) appended.
can be tweaked somewhat
.wav example to follow