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ap/xxxxx

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Brief post-xxxxx_at_piksel notes: 13:19 (2006.10.19:2 xxxxx_at_piksel_notes#48 interface_and_society_notes#2 research#97)

1] Slide 0: All hardware is necessarily closed, black boxed - another exposure (potentially falsified) by way of the data sheet enumerating instruction set, pin outs and exposed physical characteristics. A potential for reverse engineering of CPU, black box, brain or world (that process outlined).

2] From day one:

a) Reversibility, Augustine, Poincare', Friedkin

b) Tragedy and arithmetic.

c) Rationalism and the container/frame (an interiority: incompleteness, inside - first person). By way of endophysics (inside) an investigation of computer science and interiority: that computational technologies (hardware and software) enable a new thinking of the interior (enabling the science of endophysics). Thus:

(computer) hardware as a theatre of interiority along the hard/soft line of execution

d) Economies: a white rabbit economy within the CPU (for Oslo also below). The transfromation from notebook to white rabbit as computationally too expensive in terms of complexity and thus entropy. Equally an entropic world economy as outlined within Kekule'/Pynchon quote.

refs: Anaxagoras fragments, Leibniz-Clarke correspondence

e) xxxxx defined now as the active construction of a non-subject space (paradise) through noise

3] Towards Oslo: specification of a CPU:

a) Edison black maria(h) exterior CPU model. (The instruction set is cinema). Interior stills (Salo stills, exposure). Model and flattened studio. Revolving studio platform and sun opening (a hole).

b) JDM. John Dee Machines - monadic CPU, autumnal CPU (rabbit holes moss and web covered, forest, mushrooms).

sleep CPU instruction (kill cell). time machine and Alice functions. autumnal pinouts (I/O leaf indication), contained experience and sample lige coding manual for machinery...

sources:

Pieter Breugel the Elder: Tower of Babel, Allegory of Autumn (the younger?), Flemish Proverbs

FPGA/artistic CPU development: 20:51 (2006.10.10:1 research#96 xxxxx_at_piksel_notes#47 fpga#19)

our components and architecture: Alice in Wonderland, the framed NAND, a mushroom (cloud) spacing, the grid with bottom right hand corner mark shifted up and right, seasonal software and CPU, also morning, afternoon, evening and night sections accessible, Salo circles of hell, Bruegel proverb fragment, quotation,

circular memory and Atrocity exhibition instruction set.

off with her head instruction

from below also:

a) Large Glass - Duchamp. A mechanism (in space).

b) The boudoir/bedroom. A singular eye.

c) Simulated world (billiard ball universe). Kopf. Mushroom cloud neurons.

d) Doubling/ghosting of gates - twinned Alice CPU (also theatre and its double CPU)

NAND notes: 14:03 (2006.10.05:3 tech_notes#290 xxxxx_at_piksel_notes#46 research#95)

the NAND inputs must normally be logic 1 to avoid affecting the latching action, the inputs are considered to be inverted in this circuit.

it is forbidden to have both inputs at a logic 0 level at the same time. That state will force both outputs to a logic 1, overriding the feedback latching action. In this condition, whichever input goes to logic 1 first will lose control, while the other input (still at logic 0) controls the resulting state of the latch. If both inputs go to logic 1 simultaneously, the result is a "race" condition, and the final state of the latch cannot be determined ahead of time.

http://www.play-hookey.com/digital/rs_nand_latch.html again

Brief note: There is No Software (Friedrich Kittler): 20:49 (2006.10.04:3 research#94 xxxxx_at_piksel_notes#45)

[quote]

This all-important property of being programmable has, in all evidence, nothing to do with software; it is an exclusive feature of hardware, more or less suited as it is to house some notation system. When Claude Shannon, in 1937, proved in what is probably the most consequential MA thesis ever written that simple telegraph switching relays can implement by means of their different interconnections the whole of Boolean algebra, such a physical notation system was established.

When meanings come down to sentences, sentences to words, and words to letters, there is no software at all. Rather, there would be no software if computer systems were not surrounded any longer by an environment of everyday languages.

notes today (in conversation with Eva Verhoeven): 19:55 (2006.10.04:2 research#93 xxxxx_at_piksel_notes#44)

1] flip-flop time machine

(first ref in search offers:

http://www-personal.umich.edu/~reginald/timemchn.html

)

2] Alice in Wonderland CPU mechanisms - instruction set also with reference to symmetry which could be across CPU components/multiple CPUs - Alice is itself the communication mechanism (off with her head as propogated instruction). symmetry of the NAND gates in the S/R flipflop - also ahead of itself in time-machine reference above.

time-machine/Alice CPU of chained cells and gates. instruction futures

[further notes on Steele and Sussman's LispCPU]

1] Microcode:

quote [p35]:

Each of the two parts, EVAL and GC, is itself divided into two parts: registers and controller. The registers provide storage for type/pointer words, and are connected by a common bus in each part. Each controller is a finite-state machine implemented as a PLA, plus some random logic. Each PLA is organised as a micro-code ROM, addressed by a "Micro-PC" and yielding a set of control signals, including register controls and a new micro_PC indicating the next state.

signals enumerated on p36

p39. [SIMPLE Microcode] There are five kinds of operation EVAL can request from the GC (which give EVAL the step-eval signal to advance):

NOP, CAR/CDR, CONS/NCONS, RPLACD and load/store Q (one of GC's registers).

p40:

[quote]

The CONS operation accepts a car pointer from the E bus, takes the contents of Q to be the cdr pointer and then allocates a new two-word cell containing the car and cdr. A pointer to the result, with type 0 (list) is left in Q.

The Microcoded PLA is produced by software from the assembly listing (p48+) produced by the micro-assembler software from the listing (p43+)

2] The register cell

[p63]

One-bit register cell. The signal LD during O/1 loads the cell from the data bus. The signal RD during O/1 drives the bus from the cell. The cell is refreshed during O/2.

FPGA practice mimes 22:32 (2006.10.03:5 fpga#15 tech_notes#286 research#91 xxxxx_at_piksel_notes#42)

the high- low- level overlap we are interested in

in terms of a methodology of description (code, the diagram, a description of behaviour, software generation of HDL)

Lisp CPU (cell) structure - ie. representation - in the CPU: 21:19 (2006.10.03:4 tech_notes#285 fpga#14 lispcpu#2 research#90 xxxxx_at_piksel_notes#41)

after: Design of LISP-Based processors ... or, LAMBDA The Ultimate Opcode

Guy Steele and Gerald Sussman

(http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf ) 1979, MIT

see:

1] Architecture reflectes language structure

2] The overlap of high level and machine language is also dictated by necessity to manipulate program as data

3] Programs are represented as nested Lisp data structures -> as a tree of linked records subject to a recursive tree walk

4] Lists are represented by records each of which contains 2 pointers to other records - car and cdr

5] The type field associated with each pointer is used to encode opcodes and return addresses

6] p17 implementation:

7] Two consecutive words of memory hold a list cell - each word can hold a type field and an address field (an address referenced within linear memory)

8] The evaluator and the storage manager as individual processors each with a state machine controller and a set of registers

contents of any register is address field and type field

9] p32 evaluation and procedure call (type 6):

We have a 3-bit type field which provides 8 opcodes (recall 7 as quotation) - address part of a word has different function depending on type (6 is procedure call).

quote:

The evaluation of type 4 (procedure) results in a pointer to the newly allocated word pair. This pointer has type 3 (closure). The car of the pair contains the cdr of the procedure: this is the code body of the procedure. The cdr of the pair contains the current environment.

and:

A procedure call (type 6) is the most complicated... It is a list of indefinite length, chained together by cdr pointers. Each cdr pointer except the last MUST have type 0 (list). The last cdr pointer should have a zero address and a non-ZERO type. This last type specifies the operation to be performed. In CDRing down the list, SIMPLE evaluates each of the expressions in the car, saving the resulting values. These values are available as arguments to the operation to be performed.

operations in tyoe here such as car, cdr, cons, atom, progn, list and funcall

10] further question of recursion in hardware by way of closures:

A closure combines the code of a function with a special lexical environment bound to that function (scope).

Expanded from xxxxx_at_piksel release text: 17:36 (2006.09.27:1 research#86 xxxxx_at_piksel_notes#40)

After Artaud, the CPU (central processing unit) and its double mimes The Theatre and its Double. On the one hand, there is the System or entropic operation of a necessarily cynical machine for living, an atrocity exhibition, on the other hand the specification of an artistic CPU for life coding.

The CPU is the black boxed (after Edison's black mariah studio) theatre where the action takes place (also to expand further the limbs of that primal studio as our pinouts and some kind of internal sunlight, through the roof is there in the darkness - we can see all operations there; cats dancing, emotions). The script is performed and to some extent improvised (compiler and interpreter). Symbolic manipulation (implicating representation - mathematics) takes precedence; although the ALU (Arithmetic Logic Unit) takes up a good deal of space within the contemporary theatre, the script (instruction set driven) makes little reference to these props - indeed in unconventional existent designs (such as the Lisp CPU) the ALU is completely discarded.

fictional data sheet and then a specification of components (circuit diagram) 19:56 (2006.09.26:1 research#85 xxxxx_at_piksel_notes#39)

Breughel fragment (after a proverb) and mushroom (cloud)

encompassing cynicism, simulation and personal description. circles of hell. clock cycles - 24fps to 24 Hz. from below what such components could comprise - a circuit diagram. assembled pin outs and data sheets (eg. instruction sets). drafting after "the existent," and obviously existent data sheet format:

For logic eg. 4093 2-Input NAND Schmitt trigger:

Title

General Description

Features

Applications

Connection diagram

Absolute maximum ratings, Recommended operating conditions and DC electrical characteristics

Typical applications [circuit diagrams]

Typical performance characteristics [graph]

Input and output characteristics

AC test circuits and switching time waveforms

Physical dimensions (packaging)

and for Z80:

Z8400 Z80 CPU Central Processing Unit

Zilog Product Specification

FEATURES

GENERAL DESCRIPTION [+ block diagram]

Z80 MICROPROCESSOR FAMILY

Z80 CPU REGISTERS [+several figures and tables]

INTERRUPTS: GENERAL OPERATION

INSTRUCTION SET [divided as to groups, inc. summary of flag operations and symbolic notation appendices]

PIN DESCRIPTIONS

CPU TIMING [more diagrams for opcode fetch, memory read and write and so on]

AC CHARACTERISTICS

ORDERING INFORMATION

Further:

This can be specified as the data sheet(s). The simulation is imaginary code running on this hardware - based perhaps on the simulations code within SICP outlined somewhere here:

node64 - 3.3.4 - http://mitpress.mit.edu/sicp/full-text/book/book-Z-H-22.html#%_sec_3.3.4

quote:

Representing wires

A wire in our simulation will be a computational object with two local state variables: a signal-value (initially taken to be 0) and a collection of action-procedures to be run when the signal changes value. We implement the wire, using message-passing style, as a collection of local procedures together with a dispatch procedure that selects the appropriate local operation, just as we did with the simple bank-account object in section 3.1.1:

(define (make-wire)
  (let ((signal-value 0) (action-procedures '()))
    (define (set-my-signal! new-value)
      (if (not (= signal-value new-value))
          (begin (set! signal-value new-value)
                 (call-each action-procedures))
          'done))
    (define (accept-action-procedure! proc)
      (set! action-procedures (cons proc action-procedures))
      (proc))
    (define (dispatch m)
      (cond ((eq? m 'get-signal) signal-value)
            ((eq? m 'set-signal!) set-my-signal!)
            ((eq? m 'add-action!) accept-action-procedure!)
            (else (error "Unknown operation -- WIRE" m))))
    dispatch))


;; The local procedure set-my-signal! tests whether the new signal
;; value changes the signal on the wire. If so, it runs each of the
;; action procedures, using the following procedure call-each, which
;; calls each of the items in a list of no-argument procedures:

(define (call-each procedures)
  (if (null? procedures)
      'done
      (begin
        ((car procedures))
        (call-each (cdr procedures)))))



How speculative, open hardware can operate, be imagined along an 13:36 (2006.09.25:1 research#84 xxxxx_at_piksel_notes#38)

expressive line of (to be exposed) functionality - a reasoning in the evident, the means of description (software) and the EXISTENT.

random: 19:54 (2006.09.20:2 tech_notes#278 research#83 xxxxx_at_piksel_notes#37)

1) J.G Ballard's Atrocity Exhibition as closest to an (expanded, to some extent architectural) instruction set for an imaginary CPU.

yet to be codified

2) circular memory (bubble is similar).

Z80 17:50 (2006.09.20:1 tech_notes#277 research#82 xxxxx_at_piksel_notes#36)

(to test IOE expansion board)

Of interest here is the ghosting of registers:

There are two sets of six general purpose registers + accumulator and flag registers (duplicate set swopped (values exchanged) by the Exchange instruction) - "The alternate set allows operation in foreground-background mode or it may be reserved for very fast interrupt response."

(From Z80 product specification).

Further 16 -bit wide registers for index, stack pointer,program counter and split (down to 8-bit) interrupt and memory reset. Also interrupt and other flip-flops.

Instruction set:

divided into categories, and described as to mnemonics and opcode

also addressing mode

LD r,r'

EX DE,HL

INC r

NEG

NOP

ADD HL, ss

RLC r

BIT b, r

JP nn

CALL nn

IN A, (n)

see also: http://www.z80.info/#BASICS_INST

also:

Binary form of opcodes
   
  Example:   LD r,r'
 
the 8-bit binary opcode is
 
     01dddsss
 
   ...where "ddd" is a three-bit field specifying the destination,
  and "sss" is a three-bit field specifying the source.
 
is shown below as
                          r   r'
                      01 xxx xxx
 

overmapping Salo/Sadean life coding onto instruction sets

in the first instance (or with Alice/Looking Glass/Ripper whole codified mapping - to commence in process).

to start by way of circles as registers: circle of manias, circle of shit, circle of blood (with Pasolini borrowing from Dante's nine circles of hell).

Questions regarding 8 I/O to FPGA: 18:55 (2006.09.19:1 tech_notes#275 fpga#10 xxxxx_at_piksel_notes#35)

1] Do we use Schmitt triggers on I/O to provide logic levels (and then limit these with series resistor or voltage divider)?

2] or just use voltage divider in concert with 100 Ohm current limiter

3] or present both options on an expansion board

Test this for VGA throughput!

The CPU and its double: 14:24 (2006.09.16:4 xxxxx_at_piksel_notes#34 research#80)

after Artaud - the CPU of cruelty:

Of relevance:

1] TECHNIQUE

It is a question then of making the theater, in the proper sense of the word, a function; something as localized and as precise as the circulation of the blood in the arteries...

2] THE LANGUAGE OF THE STAGE:

Meanwhile new means of recording this language must be found, whether these means belong to musical transcription or to some kind of code...

As for ordinary objects, or even the human body, raised to the dignity of signs, it is evident that one can draw one's inspiration from hieroglyphic characters, not only in order to record these signs in a readable fashion which permits them to be reproduced at will, but in order to compose on the stage precise and immediately readable symbols.

On the other hand, this code language and musical trans-cription will be valuable as a means of transcribing voices.

3] THE STAGE -- THE AUDITORIUM:

We abolish the stage and the auditorium and replace them by a single site, without partition or barrier of any kind, which will become the theater of the action.

4] THE INTERPRETATION: The spectacle will be calculated from one end to the other, like a code (un langage). Thus there will be no lost movements, all movements will obey a rhythm; and each character being merely a type, his gesticulation, physiognomy, and costume will appear like so many rays of light.

and within THE PROGRAM:

  1. A Tale by the Marquis de Sade, in which the eroticism will be transposed, allegorically mounted and figured, to create a violent exteriorization of cruelty, and a dissimulation of the remainder.

allegorically mounted within gthe CPU

Also with regard to the D flip-flop: 13:10 (2006.09.16:3 tech_notes#273 fpga#9 research#79 xxxxx_at_piksel_notes#33)

Its expansion into an 8 bit register (8 simultaneously clocked flip-flops)

or, a 4-bit shift register (data is passed along the chain)

or, a 4 bit counter

Ideas/questions: 13:00 (2006.09.16:2 tech_notes#272 fpga#8 research#78 xxxxx_at_piksel_notes#32)

1] Can we directly wire analogue signal across the FPGA (say from I/O pin to VGA resistors/input)?:

Using wires and assign. To test.

2] Limiting and/or isolation. All voltages < 3.3v

3] 8 bit to 8 bit - 8 cells or 8x8 matrix of cells. life, cellular automata - that matrix.

Replicated cells composed of micro-structures below:

4] Structures and/or instructions for the CPU:

a) Large Glass - Duchamp. A mechanism (in space).

b) The boudoir/bedroom. A singular eye.

c) Simulated world (billiard ball universe). Kopf. Mushroom cloud neurons.

d) Doubling/ghosting of gates - twinned Alice CPU

e) Further: a passage, quotation, representation. observer embedded

5] Gate diagrams (NOT, AND, NAND, OR, NOR) as artefacts:

6] Gate as switch. see diagrams for transistor multiplex switch symbol in a circle.

Switching across our non-optimal models.

Elaboration of physical circuits (for playing) alongside FPGA - headers and pin extension, break out. Coincident also with software (Lisp) simulation. Machine describing itself, its own coincident layers of active voltage. Reference SICP:

A Simulator for Digital Circuits:

http://mitpress.mit.edu/sicp/full-text/sicp/book/node64.html

and streams: http://mitpress.mit.edu/sicp/full-text/sicp/book/node72.html

7] S/R set-reset flip-flop:

for HDL see: http://myhdl.jandecaluwe.com/doku.php/cookbook:ff

D. flip-flop:

Both based on the NAND gate - a principle of exclusion of the twin (the equivalent/identical binary pair - two ones). Thus of difference enabling a memory. Memory in an active circuit dependent always on current flow. In D flip-flop the clock line straddles the doubled NAND, with a replication of the signal enabling the difference.

Two snakes bite each others tails.

overlaying of high and low level possible means of description 02:22 (2006.09.15:2 research#77 xxxxx_at_piksel_notes#31)

thus FPGA as hardware simulation/black box. lacks transparency in making available (in one direction only) such parallel means. software trick. from here to Lisp language as high level machine code in directly mapping onto lispcpu

Duchamp CPU/FPGA (large glass as model) 02:18 (2006.09.15:1 research#76 xxxxx_at_piksel_notes#30)

also mushroom cloud transparency/glass component (from xxxxx cover) defined within the dual CPU schematic

from here towards the artistic instruction set (Rechnender Raum)

thematics - pursuing for FPGA internals as/is only a representation 17:22 (2006.09.14:9 tech_notes#269 research#75 xxxxx_at_piksel_notes#29)

ultimate black box:

dual CPUs ghosted...

as per waves and xxxxx_at_piksel:

After Artaud, the CPU (central processing unit) and its double mimes The Theatre and its Double. On the one hand, there is the System or entropic operation of a necessarily cynical machine for living, an atrocity exhibition, on the other hand the specification of an artistic CPU for life coding.

This is precisely the twinned instruction set we need to devise for multiple CPUs exposed as our 8 bits (one/zero), our pulses for an architecture which is somehow composed from diagrams.

piksel_fpga: 12:43 (2006.09.14:1 tech_notes#267 research#73 xxxxx_at_piksel_notes#28 fpga#5)

concurrent exposed communicative (promiscuous) (instruction?) modules

exposed by way of PWM or rather single bits which can then be output as audio or as video / composite (with sync generation in software - we have an NTSC example but colour PAL is more complex - also using small resistor ladder to output) or VGA (we have vgahdl example code which looks quite simple)

FPGA as parallel CPUs 19:23 (2006.09.13:2 xxxxx_at_piksel_notes#27 research#72 tech_notes#265 fpga#4)

multiplexed internals, and only internals data access. shared or no registers - how to specify such a design...

Visually:

1] That we can draw components and connect them within a schematic entry which ranges across low and high level (black-boxed) components both from a common library and generated from our own code (using the Create Schematic Symbol entry under Design Utilities in Process).

We can access such created components under the filepath in Categories in the schematic editor when we create say a new overarching design which specifies the connection of large-scale modules/components.

2] That we can (when we select new source) choose further modules from the IP (Coregen & Architecture Wizard) option - this are classified as to various categories, including DSP, math functions, memories, and basic elements such as counters and multiplexors.

3] At the same time using the View/Edit Placed Design (Floorplanner) (under Processes: Implement, Place and Route) we can see how the logic circuitry and I/O are assigned to the CLBs (configurable logic blocks).

From the Floorplanner toolbar we can toggle ratsnest (connection) display and zoom in and out.

Macro and micro views:

Successfully modified basic CPU code from: 17:29 (2006.09.13:1 research#71 tech_notes#264 xxxxx_at_piksel_notes#26 fpga#3)

http://www.frank-buss.de/lispcpu/index.html

which defines in Verilog output (pins) RAM (on the FPGA), program counter, registers and very basic evaluator (which evaluates hard-coded instructions) - the output in this instance is to slowly flash one LED! This example demonstrates I/O pin assignment

further SDRAM:

http://www.xess.com/appnotes/an-071205-xsasdramcntl.html

Describes/implements/wraps up an SDRAM controller core.

audio:

In the instance of audio perhaps rather than dealing with the on-board audio codec of the XSTend borad, perhaps we should make use of raw 8 bit I/O from prototype area (to primitive soundcard or schmitt trigger box) - prototype area can be connected to adjacent J4 which accesses all the prototype pins from the XSA-50 header (we can look this up in the manual for assignment).

and video:

We can use VGA (some cores/sample projects - note that a useful experiment would be to send voltages (0->0.7v) for RGB signals raw to monitor... or we can use video out on XSTend board, or just resistor ladder from XSA-50 data pins as suggested in ntsc example on:

http://www.xess.com/ho03000.html

where we find all project examples.

a) re-evaluate basic workflow (for XESS boards, say counter code 18:45 (2006.09.12:1 research#70 tech_notes#263 xxxxx_at_piksel#2 fpga#2)

and I/O)

Boards used:

XSA-50 development board (Xilinx XC2S50 FPGA (Spartan II/2), 128K Flash memory for FPGA bitstream, 8 Megabyte DRAM).

and XSTend board V3.0 (XST-3.0) from XESS

(stereo codec, dual channel analogue I/O, video decoder, ethernet, usb, rs-232, ide)

see:

http://stewks.ece.stevens-tech.edu/CpE487-S05/HomeworkF04/:/hlisiteB/NotesForXessBoard.html

... example code is in VHDL.

see also free_fpga_guide for some background and install of Xstools from XESS:

link: Xstools RPM: http://www1.cs.columbia.edu/~sedwards/software/xstools-4.0.3-1.i386.rpm

x____

stages:

0] Re-install WebPack (this version 8.2.02i) from Xilinx:

http://www.xilinx.com/webpack/

1) using web-based installer which is a very lengthy process.

2) then we use the opening lines from the shell script at:

http://panteltje.com/panteltje/fpga/index.html

(which outlines solely commandline use of Xilinx toolset.)

mkdir /usr/local/lib/xilinx/
cp ~/Xilinx/bin/lin/*.so /usr/local/lib/xilinx/
echo /usr/local/lib/xilinx >> /etc/ld.so.conf
ldconfig 

and:

export XILINX=/root/Xilinx

then we can run bin/lin/xst commandline program

for full GUI:

bin/lin/ise

1] connect parallel port. start laptop. power up XSA-50 board. launch xstest from commandline to test:

xstest -b xsa-50

launch WebPack (command: Xilinx/bin/lin/ise)

2] create new project (here we define the device and the design flow)

Over the above tutorial and past work there is now a new project wizard - we skip over behaviourals and ports:

we create leddec (LED decoder as per tutorial)

3] insert VHDL module (describe/enter (in) VHDL code)

Double click on leddec in sources and edit templated source code.

4] synthesize - highlight module filename .vhd

Click on Synthesize-XST in Processes. Successful

5] implement design process eg. place and route

Highlight and then select Implement Design in Processes

6] new source - implementation constraints (I/O pins assigned as below). then Create Timing Constraints, then port tag:

Select leddec in Sources, right click and select New source following the example names as leddec_ucf, associate this with leddec and then expand User Constraints item in processes to access Create Timing Constraints - once there (new window opened for constraints editor) we can select the Ports tab to access port name attributed in our VHDL and hopefully assign pins (location) as gathered from XESS manual.

In this instance unable to enter text into Location field...

Rather we must choose Assign Package Pins from User Constraints in Process and enter pins here - then these can be double-checked in the above editor.

7] rerun implement design

Successful!

8] generate bitstream - Generate Programming File

Successful!

9] use xsload to download over parallel port - .bit file (in our project file as defined:

xsload -b xsa-50 -fpga ~/piksel/fpgatests/leddec/leddec.bit

Configure FPGA:
Downloading leddec.bit:fst field: ignoring 9 bytes
100%

(strangely enough produces an error when run from eshell)

in the first example LED decoder from the above URL the xsport utility is used to send bit patterns to the parallel port:

eg:

xsport 101

b) understanding of RAM and I/O pin access with XTEND board - again using example code. also perhaps audio and simple video

I/O pin access (which is used within Implementation Constraints (ucf file)) is simply a matter of looking up pin assignments in the manual. The example above also gives some advice.

Notes on: 20:45 (2006.09.11:4 tech_notes#262 research#69 lispcpu#1)

Design of LISP-Based processors ... or, LAMBDA The Ultimate Opcode

Guy Steele and Gerald Sussman (http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf ) 1979, MIT

To quote from the opening abstract:

We present a design for a class of computers whose 'instruction sets' are based on LISP. LISP, like traditional stored-program machine languages and unlike most high-level languages, conceptually stores programs and data in the same way and explicitly allows programs to be manipulated as data. LISP is therefore a suitable language around which to design a stored-program computer architecture. LISP differs from traditional machine languages in that the program/data storage is conceptually an unordered set of linked record structures of various sizes, rather than an ordered, indexable vector of integers or bit fields of fixed size. The record structures can be organised into trees or graphs. An instruction set can be designed for programs expressed as such trees. A processor can interpret these trees in a recursive fashion, and provide automatic storage management for the record structures.

further - an architecture and an instruction set are specified, fabrication of a VLSI prototype microprocessor is described.

1) LISP as a high-level machine language. Given that "LISP reflects the structure of program expressions in the structure of the data which represents the program." and also given that data and programs are equivalent and can equally be manipulated (within the "incestuous" realm of compilers and interpreters).

2) Tree structure rather than linear vector of instructions which can be indexed using counters and the like. Evaluation by recursive tree-walk.

3) Lisp atoms and lists are described in fine detail with examples prior to the exposition of a meta-circular LISP interpreter (ie. it is written in LISP and can interpret itself).

4) APPLY within this simple interpreter... in the case of primitive procedures:

"... primitive symbols are not to be confused with the atomic symbols used as their names. The actual procedure involved in the combination (car x) is not the atomic symbol CAR, but rather some bizarre object (the value of the atomic symbol CAR) which is meaningful only to PRIMOP-APPLY."

(thus further into the appendix the magic of execution is microcoded)

5) State machine implementation:

An interpreter in the form of a state machine controller. (rendering explicit as a control mechanism that which the recursive LISP interpreter hides - state information that must be saved on each recursive invocation).

Registers and a list memory system.

The evaluator in Lisp has five global registers which simulate the registers of a machine

EXP - hold expression or parts of under evaluation
ENV - holds pointer to environment structure (context)
VAL - value developed in evaluation of expressions
ARGS - list of evaluated arguments
CLINK - pointer to top of the list structure which is the control
stack

Further LISP code such as EVAL-DISPATCH implements the simulation

6) Representing LISP data.

"Lists are normally represented by records each of which contains two pointers to other records. One pointer is the car and the other is the cdr."

(A (B C) D) becomes

 _ _      _ _      _ _
|.|.+ -> |.|.+ -> |.|.+--> NIL
 - -      - -      - -
 |        |        |
 v        |        v
 A        v        D
          _ _      _ _
         |.|.+ -> |.|.+--> NIL
          - -      - -
          |        |
          v        v
          B        C

Pointer representation is unimportant. We give pointer to memory system and it returns the context of the record pointed to. A type field is associated with each pointer.

7) The state machine implementation is combined with typed pointer dispatch to form an interpreter which can be implemented in hardware (p. 15)

8) Storage management:

The system is divided into:

a) a storage system which "provides an operator for he creation of new data objects and also other operators (such as pointer traversal) on those objects."

b) EVAL (program interpreter) which "executes programs expressed as data structures within the storage system"

in classic Von Neumann style.

The storage manager here makes a "finite vector memory appear to the evaluation mechanism to be an infinite linked-record memory". Thus a garbage collector is implemented.

9) Physical layout of the prototype processor

"The evaluator and the storage manager are each implemented in the same way as an individual processor. Each processor has a state-machine controller and a set of registers. On each clock cycle the state-machine outputs control signals for the registers and also makes transitions to a new state."

...

"The contents any register is a pointer (8 bits in the prototype) and a type field (3 bits in the prototype). The registers of a processor are connected by a common bus (E bus in the evaluator, G bus in the storage manager)

....

"Each state-machine controller consists of a read-only memory (implemented as a PLA), two half registers (?) (clocked inverters, one at each input and one at each output), and some random logic (eg. for computing the next state)... two phase non-overlapping clock signals..."

1- registers are clocked. next state is computed

2- next-state signals appear and are latched

all signals from the controllers can be multiplexed onto twelve probe lines

10) Discussion

There is no ALU.

Possible addition of complex processors/devices on the external memory bus with LISP processor serving as controller.

At the same time talks of a layered approach wherein a line can be drawn at arbitrary points within a tower of abstraction = a boundary between evaluator and storage manager

"... a hierarchy of interpreters running in [a] virtual machine. Each layer implements a virtual machine within which the next processor up operates."

such a boundary also exhibits an arbitrary distinction between hardware and software. also the overlap:

"Each of the layers in this architecture has much the same organisation: it is divided into a controller ("state machine") and a data base ("registers"). There is a reason for this. Each layer implements a memory system and so has state; this state is contained in the data base (which may be simply a small set of references into the next memory system down (own note: no operation but only a mapping)). Each layer also accepts commands from the layer above it, and transforms them into commands for the layer below it; this is the task of the controller."

also in talking of analogies between common CPU and CPU here:

"We may loosely say that there are two addressing modes in this architecture, one being immediate data (as in a variable reference), and the other being a recursive evaluation. In the latter case, merely referring to an operands automatically calls for the execution of an entire routine to compute it!"

11) History of VLSI implementation

Typed pointers treated as instructions, with the types as "opcodes" to be dispatched on by a state machine...

Rough sketch of building blocks:

PLA library array cells, simple replicated register cells assembled using (LISP-based) software

12) Conclusion

A CPU "... organised purely around linked records, especially in that the instruction set is embedded in the organisation."

Finally concludes that just as the LISP tree data representation informs this particular instruction set and thus the CPU architecture (for it is not just a question of representation but also changing the means of manipulation), so other representations (for example graphs) or storage organisations could be examined.

13) Appendix - Prototype Lisp Processor Technical Specifications

For later examination.

so far... The Instruction Set:

The 3 byte type field supplies 8 "opcodes":

from 0=constant list to 7=quoted constant

Address part of the word has different purposes dependent on type.

Procedure call (type 6) is the most complicated of all:

"It is a list of indefinite length, chained together by CDR pointers

xx_____

Also of note here is the use of transistors and resistors (in this case depletion-mode transistors) which can be used to construct logic gates.

see also GC probe mux and multiplexor p61,62 - a grid of wires with transistor across for probes

register cell p 63

FPGA research plans:: 17:26 (2006.09.11:3 tech_notes#261 research#68 fpga#1 xxxxx_at_piksel_notes#23)

Notes on: 15:30 (2006.09.11:1 tech_notes#259 xxxxx_at_piksel_notes#22 research#67)

The Design of an M6800 LISP Interpreter, S Tucker Taft, BYTE August 1979

(notes for piksel, instruction sets as steps towards Lisp CPU or any kind of artistic CPU - an examination of hardware-based means of representation. At what point the necessary reduction (or why it is considered as such) into hardware makes sense. Or to keep all levels as a simultaneity. Comparison of high-level with instruction sets. At the same time some way - borrowing from the Lisp CPU - that we can eavesdrop in audio fashion on all internals of the CPU, not just registers a la self.c (own code see software) but also data paths. Indeed if such paths ans such an exposure are implied through a parallel switching architecture. The FPGA is attractive precisely as RECONFIGURABLE architecture or matrix rather than as RECONFIGURED.)

1) Underlying representation of lists using dotted pairs (two address cells). The left cell points to the first element of a list, and the right cell to the rest of the list. NIL is used to signify end of the chain. CONSing two atoms gives a dotted pair with CDR of final dotted pair as non-NIL atom.

(see also diagrams on:

http://www.gigamonkeys.com/book/they-called-it-lisp-for-a-reason-list-processing.html

)

2) READ, EVAL and PRINT loop

Internal representation of the list (the program) is called a form here - the form is evaluated according to the convention that the first element of such a list specifies a function, with the rest of the list as arguments.

3) Into implementation:

BIGLUP LDX PRMPAT  get prompt atom
       JSR PATOM   print the atom
       JSR READ    read the form - result is in x reg
       JSR EVAL    eval the form - result is in x reg
       JSR PRINT
       BRA BIGLUP

PATOM is a subroutine, also used by PRINT when a form is tested as an atom.

M6800 index (X) register - 16 bits long use for all object representations/forms

Dotted pairs must hold two forms - thus 32 bits (4 consecutive memory bytes)

Internal representation for atoms:

For symbolic atoms two items of information are needed:

thus 4 bytes chosen with first 2 as memory address of print name and third of fourth holding value (form) of the atom

A way to distinguish dotted pairs from atoms is needed:

In this instance all dotted pairs and atoms are aligned on 4 byte boundaries which means that we can use the lowest two bits 00 01 to encode type and garbage collection (GC) information.

With numeric atoms name determines value and hence only name (or value) needs to be specified. Representation was chosen with high order bit set, 14 bits numeric value and 1 for GC (seeing as only 0000 through 7FFF is used for atoms and dotted pairs storage bit so when forms specify this high order bit is free.

Special representation for the NIL atom High order byte is zero (which rules out 256 byte page starting at zero).

x_______

A linked list (called OBLIST) of all defined symbolic atoms is used for example by READ and also the EQ function. READ checks prior to allocating 4 byte cell for atome of given print name. If found, returns form specifying the pre-existing atom. Otherwise, copies name into name storage area, allocates 4 byte cell, inits left cell to point to name and right to NIL and returns form.

x_____

READ function

Builds up internal representation - allocating dotted pairs and atoms. If expression is a list READ returns the first dotted pair.

RATOM does the work of allocating new cells as above. Deals with parentheses with recursive calls to READ.

(code p143)

PRINT function

Takes a single form as argument, and types the value as fully parenthesised LISP expression.

EVAL function

The heart of the matter.

EVAL accepts one form as argument and evaluates it according to the convention:

"the value of NIL is NIL, the value of a numeric atom is itself, the value of a symbolic atom is the form associated with the atom, and the value of a list is determined by applying the function specified by the CAR of the list to the list of arguments which make up the CDR of the list."

SUBRs and LAMBDAs: SUBRs as built in functions written in machine code (eg. CAR< CDR< PATOM). LAMBDAs are user defined.

The system here treats the bytes which make up the machine code of the SUBR as the print name of the atom. SUBR specified with dotted pair and car as atom SUBR. Machine code is also prefixed with a special string.

(p147 code listing)

Pask and electrochemical computing: 21:32 (2006.09.05:2 tech_notes#255 xxxxx_at_piksel_notes#21 research#66)

http://homepage.mac.com/cariani/:/PaskPaper.html

http://www.armyofclerks.net/#dendrite

(game of life) in FPGA: 20:39 (2006.08.31:4 tech_notes#254 research#65 xxxxx_at_piksel_notes#20)

http://www.jefspalace.be/digital/game%20of%20life/index.htm

also:

http://www.stanford.edu/class/ee183/tao.shtml (for XESS board and Verilog)

no instruction set but collection of singular parallel instruction/data streams - switching between these (FPGA implementing a reconfiguration itself)

a new architecture

Verilog and VHDL (both HDLs = hardware description languages): 20:20 (2006.08.31:3 tech_notes#253 research#64 xxxxx_at_piksel_notes#19)

Very high speed integrated circuit Hardware Description Language.

description of behaviours (component for example an AND gate) as an entity/architecture pair are combined

links:

http://esd.cs.ucr.edu/labs/tutorial/

http://instruct1.cit.cornell.edu/Courses/ee475/

http://www.arl.wustl.edu/~jst/cse/260/dp/cpu.html

Easier to learn (closer to a programming language), offers variety levels of abstraction

links below:

or even:

Bill Seaman (http://digitalmedia.risd.edu/billseaman/pdf/tb_endoNeo-1.pdf )

Konrad Zuse (ftp://ftp.idsia.ch/pub/juergen/zuserechnenderraum.pdf )

Guy Steele and Gerald Sussman (http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf )

Building blocks of an FPGA

logic gates, lookup table, flip-flops (memory)

"The configurable logic blocks (CLBs) in the FPGA can be further decomposed into look-up tables (LUTs) that perform logic operations."

running in parallel. a question of clocks and frequency

further FPGA/CPU links:

http://members.optushome.com.au/jekent/Micro8/Micro8.html

(see Verilog as HDL: http://www.kuro5hin.org/story/2004/2/27/213254/152 )

http://www.frank-buss.de/lispcpu/ 22:34 (2006.08.21:6 tech_notes#245 research#62 waves#2 xxxxx_at_piksel_notes#17)

data paths (registers and operations) and the controller 22:21 (2006.08.21:4 tech_notes#243 research#61 waves#1)

for a CPU:

(again)

http://www.async.ece.utah.edu/~myers/nobackup/ee3700_99/xilinx/lab8.html

.#16 (from riga presentation notes) 13:01 (2006.08.21:2 research#59 xxxxx_at_piksel_notes#16 life_coding#8)

what is life coding - as expressed by the design of a CPU, the design of a simulations machinery after Daniel Galouye (Simulacron 3 - reworked by Rainer Werner Fassbinder as a pure filmic description of Rossler's endophysics, head, eye and camera in electronic transition - zero domain crossing is your reference)?

our model for the CPU, and the question that the idea of the CPU renders is precisely where we draw the line, where we mark a division or passage between hardware and software, a false and delirious division which could be imagined as between the analogue and the digital - the digital and/as a reining in of the analogue - not so much in terms of discretisation but of a forbidden zone far from zero crossing - a forbidden zone which precisely the Schmitt trigger is designed to out-sketch, to eliminate, drawing that wave as squared, as regular noise. A different time-frame for a digitised sine wave which can also stand as a modulation. what carrier?

so there is this drawing of the line which is a question of instructions also, of microcodes which express the most basic operations which can be achieved in terms of raw hardware, of gates opening and closing around a machinery. on the bus. a drawing of the line which is a question of virtual machines - of how that instruction is understood by an underlying machinery. an old tale of abstractions which fits language. the same line-drawing which articulates a progression into high-level code by way of the (termed by computer scientists as incestuous - within a bachelor realm) interpreter (we will meet again under the terms of evaluation) or the compiler.

such allows us to choose as a model for the CPU, the design of a LISP-based processor undertaken by Guy Steele and Gerald Sussman in the 70s at MIT AI labs. the idea here of a layering down to hardware which mimes the same principles or ideas, an equivalence of data and code which marks the incestuous role-play of the interpreter (code into action, into electricity reflexively) and allows for the entry of quotation; quotation implying a system of notation which can equally well be the brackets of the so-called Lisp S-expressions, or ones and zeroes.

http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf

(Lisp typified as high-level machine language)

how we can proceed from the specification of a high-level programming language - conceived a means of active process description and symbolic manipulation - the latter as key to the electric process described here - rather than as, say, a spreadsheet - proceed from this specification to the description in a (software generated) circuit diagram for that which will run or mime this language.

how does quotation take place in hardware?

CPU/instruction sets - Lisp CPU (Steele, Sussman 1979) 20:29 (2006.08.20:2 research#58 xxxxx_at_piksel_notes#15 tech_notes#240)

mimes same design principles across layered vm segments

low level/high level

(Lisp typified as high-level machine language)

further simulations-machinery operates as parallel such micro-/macro-equivalnce CPUs

from SICP: 11:01 (2006.08.11:1 research#55 xxxxx_at_piksel_notes#14 tech_notes#214)

In a similar way, we can regard the evaluator as a very special machine that takes as input a description of a machine. Given this input, the evaluator configures itself to emulate the machine described. For example, if we feed our evaluator the definition of factorial, as shown in figure x, the evaluator will be able to compute factorials.

http://mitpress.mit.edu/sicp/full-text/sicp/book/node81.html

also:

In this chapter (five) we will describe processes in terms of the step-by-step operation of a traditional computer. Such a computer, or register machine, sequentially executes instructions that manipulate the contents of a fixed set of storage elements called registers. A typical register-machine instruction applies a primitive operation to the contents of some registers and assigns the result to another register. Our descriptions of processes executed by register machines will look very much like “machine-language” programs for traditional computers. However, instead of focusing on the machine language of any particular computer, we will examine several Lisp procedures and design a specific register machine to execute each procedure. Thus, we will approach our task from the perspective of a hardware architect rather than that of a machine-language computer programmer. In designing register machines, we will develop mechanisms for implementing important programming constructs such as recursion. We will also present a language for describing designs for register machines. In section 5.2 we will implement a Lisp program that uses these descriptions to simulate the machines we design.

instruction sets in relation 21:34 (2006.08.10:6 tech_notes#213 xxxxx_at_piksel_notes#13 research#54)

to open hardware - data sheet exposes instruction set and opcodes (trusted computing in all senses) - or a form of reverse engineering (for reality CPU?) takes place by way of (aural) experiment. from the instruction set we can extrapolate an architecture

by way of SICP:

p492:

"To design a register machine (a traditional computer) we must design its data paths (registers and operations) and the controller that sequences these operations.

data paths as diagram

state machine as controller (?)

5.2 a Lisp program that uses such paired descriptiuons to simulate the machine

see also p384/5 (data as programs):

[fill in]

and p343+ - streams as signals (for further research on piksel/xxxxx overmapping - simulation of RC network and analogue system in relation also to time)

for xxxxx_at_piksel:: 18:35 (2006.08.10:3 tech_notes#210 xxxxx_at_piksel_notes#12)

a continuous plane - or synchronous view of vertical (abstraction) hierarchy by way of overlap held:

1) FPGA (software)

2) Instruction sets - a transition or barrier for abstraction/ hidden

3) simulation (software)

as for below 18:27 (2006.08.04:3 xxxxx_at_piksel_notes#11 tech_notes#184 research#42)

see Victor's 4-bit processor:

... the heart of the processor: a microcode instruction sequencer. This circuit turns instruction codewords into control signals that activate other processor components which in turn perform operations.

and this sequencer:

http://www.vttoth.com/vicproc_seq.htm

Perhaps the most interesting question with any processor is this: how do instruction codes (i.e., code words in memory) get turned into electrical signals that in turn trigger various events in the processor, altering its internal state?

as for address decoding this can be done a la ap0201 making use of 74LS573 latch which latches top 8 bits of (15 bit) address and then we can deliver bottom 7 bits straight from the PIC processor. then tell it to read or write to that address (within 32K NVRAM) - program and/or data memory.

CPU organisation notes::

so far we can read and write opcodes/data to/from memory

this is the work of the control unit which opens and closes gates to effect the circuits of execution

(to/from memory:

http://www.cellmatrix.com/entryway/products/applications/smallMemory.html

)

1. Fetch the instruction into an internal instruction register

2. Decode the instruction

3. Select (calculate) the operands (registers) used by the instruction

4. Fetch the operands from memory (CISC only)

5. Execute the instruction

6. Store (write) the result back in the proper place.

1) registers: (immediate storage), accumulator (or define registers such as memory address, memory data, instruction register

D Flip-flop or D Latches

from Wikipedia ( http://en.wikipedia.org/wiki/User:B_rip )::::

The register operations of a digital system are defined by:

• The set of registers in the system

• The microoperations that are performed on the data stored in the registers

• The control that “orchestrates” the sequence of operations in the system

and:

Just as assembly language reflects the architecture of the individual microprocessor, the registers and the elementary operations performed on the data stored in the registers (called microoperations) are described using a “symbolic notation” referred to as a Register Transfer Language (RTL).

A Hardware Description Languages (HDL), like Verilog, also allows us to describe these microoperations. When taken in the context of an HDL behavioral description, these microoperations are collectively known as the Register Transfer Level (RTL). To avoid confusion, for this class, RTL will always be defined as “Register Transfer Language” and alternative terminology (i.e., Dataflow and Behavioral) will be used when describing a Verilog description of a microoperation.

D ← A + B

In this simple example, RTL notation is used to show the contents of registers A and B acted upon by the addition operator with the result placed into register D.

register file and ALU is known as data path.

2) control unit: microcode sequencer (pulses of microcode/data to ALU) - control gates decode the instruction sending signals to ALU or memory - circuits are reconfigured

microprogram - stored sequences in control memory - further abstraction

or hardwired

3) ALU (as below) - combinatorial logic is used - encoded by x bits to effect required arithmetic operation

MUXes and decoders and gates

4) address decoding and memory

5) program counter - binary counter

instruction set is translated into opcodes 17:06 (2006.08.04:2 xxxxx_at_piksel_notes#10 tech_notes#183 research#41)

how implemented on CPU?

fetch instruction (from memory address - question of addressing), decode, fetch result, increment program counter

and on an FPGA?

question also of how address decoding functions

opcode is selection of a circuit with ref to the ALU 16:19 (2006.08.03:7 research#38 xxxxx_at_piksel_notes#9 tech_notes#180)

for example:

http://www.cellmatrix.com/entryway/products/applications/8bitALU.html

and:

http://www.cs.trinity.edu/About/The_Courses/cs301/04.computer.circuits/04.comp.cir.html

is interesting as it uses Scheme to model the ALU/logic

Konrad Zuse 16:04 (2006.08.03:6 research#37 xxxxx_at_piksel_notes#8 tech_notes#179)

http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/20-relays/zuseadd.html

(but need to find more schematics)

http://web.cecs.pdx.edu/~harry/Relay/Overview.txt

http://hjs.geol.uib.no/zuse/zusez1z3.htm

Calculating Space. Rechnender Raum. Zuse - cellular automata

cellular automata and fpga as possibility. language.

VLSI: 11:32 (2006.08.03:1 research#36 xxxxx_at_piksel_notes#7)

very large-scale integration

http://lsiwww.epfl.ch/LSI2001/teaching/webcourse/toc.html

particularly:

http://lsiwww.epfl.ch/LSI2001/teaching/webcourse/ch06/ch06.html

that a schmitt trigger or circuit composed of 19:53 (2006.07.30:4 research#29)

can obviously be modelled or simulated in software

this relation of hardware and simulation (running on hardware) for piksel/research as it relates also to (an) interface

see also SICP p273: A Simulator for Digital Circuits

[]- 15:03 (2006.07.30:1 xxxxx_at_piksel_notes#5 research#27)

that the interface can solely be a word, any form of signal under the sign of a protocol; no physical connection is implied.

1] to test GRAF 8 bit computer as artefact 11:43 (2006.07.28:1)

[seems to be working though needs a heatsink on the 7805-based PSU - simple tests loading code from EPROM run].

next question is how to input code and save this!

2] electronics - use of 74LS244/245 as current amplifiers

74*04 or 74*240 as plain old invertor

others of interest include 74LS244, 374 buffers

further circuits:

a) relay-driven AND, OR GATES on boards (for piksel artefacts)

b) see also transsitor ODER-Schaltung and UND-Schaltung

c) capacitor and coil as oscillators

x- x-

3] also lisp interpreter for z80 research

brief search refs:

http://www.mcjones.org/dustydecks/archives/2005/06/08/41/

http://community.computerhistory.org/scc/projects/LISP/

http://www.informatimago.com/develop/lisp/lisp15-0.0.tar.gz

further ideas:

code as artefact also

lisp-processor (cells) in FPGA:

more on this on research and particularly xxxxx_at_piksel

Design of LISP-Based Processors or, SCHEME: A Dielectric LISP or, Finite Memories Considered Harmful or, LAMBDA: The Ultimate Opcode

https://www.gelato.unsw.edu.au/archives/comp-arch/2006-May/000903.html

http://del.icio.us/azz/fpga

MyHDL - Python HDL for generation of Verilog: http://myhdl.jandecaluwe.com/doku.php/cookbook:ff

CADR machine: http://home.comcast.net/~prunesquallor/memo528.htm

also for piksel to have some kind of digital artefacts for assembly 20:10 (2006.07.05:2)

relay-based logic boards, transistor-based logic, 74LS stuff, finally FPGA

LISPCPU in an FPGA 20:02 (2006.07.05:1)

or at least hinting towards development of some kind of computational unit with an alternative architecture: for example hardware in some way mirroring the cons cells of lisp. binary hardware logic mirroring some other structure itself. in silicon.

from here:

http://constantly.at/blog/2006/07/05/ecoop-06-lisp-workshop-in-brief/

to here:

https://www.gelato.unsw.edu.au/archives/comp-arch/2006-May/000903.html

and then to these:

http://www.frank-buss.de/lispcpu/

http://vaxbusters.org/workshop/home.xml (and links also to transputer implementations within an FPGA)

FPGA as one potential element for speculative hardware 15:53 (2006.06.27:1)

another would be Tom Schouten's PURRR:

http://zwizwa.goto10.org/darcs/brood/doc/purrr.txt

xx_

FPGA workflow

Current equipment consists of:

XSA-50 board

XSA-3S1000 board http://www.xess.com/prod035.php3

with a Spartan-3 XC3S1000 FPGA.

XESS XStend Board

all from XESS.

VHDL and Verilog hardware descriptions

synthesis in language -> netlist -> bitstream -> uploading

using Xilinx webPACK under Linux and XSTOOLS (from Xess for uploading)

xx__

Life in an FPGA

Use of the FPGA's Configurable Logic Blocks (CLs) as cells (CLBs incorporate look-up tables (LUTs) which implement the specified logic)

see also

http://www.xess.com/fpgatut.htm

question is how an instruction set is implemented IN logic gates

http://www.fpgacpu.org/usenet/life.html

xx___

see free_fpga_guide