-->

1010/ap

__

new research areas: 16:01 (2006.06.27:3 tech_notes#141 research#1)

also allied to this is high-res/frequency sampling a la

http://www.domenech.org/bt878a-adc/index-e.htm

Sadean (for life coding) systematics encoded within 15:58 (2006.06.27:2 life_coding#5 tech_notes#140)

prolog-like/kodiak-style system

by way of Klossowski's outline: Outline of Sade's system in Sade My Neighbour

FPGA as one potential element for speculative hardware 15:53 (xxxxx_at_piksel_notes#1)

another would be Tom Schouten's PURRR:

http://zwizwa.goto10.org/darcs/brood/doc/purrr.txt

xx_

FPGA workflow

Current equipment consists of:

XSA-50 board

XSA-3S1000 board http://www.xess.com/prod035.php3

with a Spartan-3 XC3S1000 FPGA.

XESS XStend Board

all from XESS.

VHDL and Verilog hardware descriptions

synthesis in language -> netlist -> bitstream -> uploading

using Xilinx webPACK under Linux and XSTOOLS (from Xess for uploading)

[import LUD article here]

xx__

Life in an FPGA

Use of the FPGA's Configurable Logic Blocks (CLs) as cells (CLBs incorporate look-up tables (LUTs) which implement the specified logic)

see also

http://www.xess.com/fpgatut.htm

question is how an instruction set is implemented IN logic gates

http://www.fpgacpu.org/usenet/life.html