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(game of life) in FPGA: 20:39 (2006.08.31:4 tech_notes#254 research#65 xxxxx_at_piksel_notes#20)

http://www.jefspalace.be/digital/game%20of%20life/index.htm

also:

http://www.stanford.edu/class/ee183/tao.shtml (for XESS board and Verilog)

no instruction set but collection of singular parallel instruction/data streams - switching between these (FPGA implementing a reconfiguration itself)

a new architecture

Verilog and VHDL (both HDLs = hardware description languages): 20:20 (2006.08.31:3 tech_notes#253 research#64 xxxxx_at_piksel_notes#19)

Very high speed integrated circuit Hardware Description Language.

description of behaviours (component for example an AND gate) as an entity/architecture pair are combined

links:

http://esd.cs.ucr.edu/labs/tutorial/

http://instruct1.cit.cornell.edu/Courses/ee475/

http://www.arl.wustl.edu/~jst/cse/260/dp/cpu.html

Easier to learn (closer to a programming language), offers variety levels of abstraction

links below:

or even:

reading list for piksel: 13:59 (2006.08.31:2 research#63 tech_notes#252 xxxxx_at_piksel_notes#18)

Bill Seaman (http://digitalmedia.risd.edu/billseaman/pdf/tb_endoNeo-1.pdf )

Konrad Zuse (ftp://ftp.idsia.ch/pub/juergen/zuserechnenderraum.pdf )

Guy Steele and Gerald Sussman (http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf )

Building blocks of an FPGA

logic gates, lookup table, flip-flops (memory)

"The configurable logic blocks (CLBs) in the FPGA can be further decomposed into look-up tables (LUTs) that perform logic operations."

running in parallel. a question of clocks and frequency

further FPGA/CPU links:

http://members.optushome.com.au/jekent/Micro8/Micro8.html

(see Verilog as HDL: http://www.kuro5hin.org/story/2004/2/27/213254/152 )

vague IDE -> PIC idea for hard disk audio recording 11:31 (tech_notes#251)

some hints:

http://www.pjrc.com/tech/8051/ide/wesley.html

http://server.barrymichels.com/ide/

http://www.compuphase.com/mbr_fat.htm