-->

ap/xxxxx

__

a) re-evaluate basic workflow (for XESS boards, say counter code 18:45 (2006.09.12:1 research#70 tech_notes#263 xxxxx_at_piksel#2 fpga#2)

and I/O)

see:

http://stewks.ece.stevens-tech.edu/CpE487-S05/HomeworkF04/:/hlisiteB/NotesForXessBoard.html

... example code is in VHDL.

x____

stages:

1) using web-based installer which is a very lengthy process.

2) then we use the opening lines from the shell script at:

http://panteltje.com/panteltje/fpga/index.html

mkdir /usr/local/lib/xilinx/
cp ~/Xilinx/bin/lin/*.so /usr/local/lib/xilinx/
echo /usr/local/lib/xilinx >> /etc/ld.so.conf
ldconfig 

and:

export XILINX=/root/Xilinx

then we can run bin/lin/xst commandline program

for full GUI:

bin/lin/ise

in the first example LED decoder from the above URL the xsport utility is used to send bit patterns to the parallel port

b) understanding of RAM and I/O pin access with XTEND board - again using example code. also perhaps audio and simple video

I/O pin access (which is used within Implementation Constraints (ucf file)) is simply a matter of looking up pin assignments in the manual. The example above also gives some advice.

more to follow above...