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ap/xxxxx

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Brief post-xxxxx_at_piksel notes: 13:19 (2006.10.19:2 xxxxx_at_piksel_notes#48 interface_and_society_notes#2 research#97)

1] Slide 0: All hardware is necessarily closed, black boxed - another exposure (potentially falsified) by way of the data sheet enumerating instruction set, pin outs and exposed physical characteristics. A potential for reverse engineering of CPU, black box, brain or world (that process outlined).

2] From day one:

a) Reversibility, Augustine, Poincare', Friedkin

b) Tragedy and arithmetic.

c) Rationalism and the container/frame (an interiority: incompleteness, inside - first person). By way of endophysics (inside) an investigation of computer science and interiority: that computational technologies (hardware and software) enable a new thinking of the interior (enabling the science of endophysics). Thus:

(computer) hardware as a theatre of interiority along the hard/soft line of execution

d) Economies: a white rabbit economy within the CPU (for Oslo also below). The transfromation from notebook to white rabbit as computationally too expensive in terms of complexity and thus entropy. Equally an entropic world economy as outlined within Kekule'/Pynchon quote.

refs: Anaxagoras fragments, Leibniz-Clarke correspondence

e) xxxxx defined now as the active construction of a non-subject space (paradise) through noise

3] Towards Oslo: specification of a CPU:

a) Edison black maria(h) exterior CPU model. (The instruction set is cinema). Interior stills (Salo stills, exposure). Model and flattened studio. Revolving studio platform and sun opening (a hole).

b) JDM. John Dee Machines - monadic CPU, autumnal CPU (rabbit holes moss and web covered, forest, mushrooms).

sleep CPU instruction (kill cell). time machine and Alice functions. autumnal pinouts (I/O leaf indication), contained experience and sample lige coding manual for machinery...

sources:

Pieter Breugel the younger: Tower of Bable, Allegory of Autumn, Flemish Proverbs

For reference: 12:12 (2006.10.19:1 fpga#20 tech_notes#294 interface_and_society_notes#1)

XSTEND and own FPGA expansion board pin details:

own interface:

8 IN 8 OUT (IN into voltage divider and both by way of 74hc245 transceiver

TOP (4 pin VGA interface)

1: GND

2: 5V

3: VSYNC

4: HSYNC

FPGA XSTEND: ref to FPGA pins (xsa-200/xsa-3s1000):

VERTICAL LINE FROM TOP:

0-7: IN

0: A5/F15

1: F14/P12

2: P9/J1

3: R9/H1

4: T9/H3

5: T7/G2

6: B9/K15

7: A9/K16

0-7: OUT

0: M7/E2

1: R6/E1

2: N7/F3

3: P7/F2

4: R7/G4

5: T14/G3

6: P8/G1

7: T8/H4

(both above as bi-directional I/O ports - extra 16 IN should be available)

0-7: MISC

1: GND

2: 5V

3: VSYNC

4: HYSNC