ap/xxxxx

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FPGA expansion board using 74LS245s is working fine 17:57 (2006.10.05:6 tech_notes#293 fpga#18)

but all inputs must be tied down (by connection to FPGA)

Verilog code for D flip-flop: 17:39 (2006.10.05:5 fpga#17 tech_notes#292)

http://www.stanford.edu/class/ee183/verilog/183lib.v

Use of 4 transistor based 2x NAND R-S flip-flop for audio 14:59 (tech_notes#291)

with 10K resistors on inputs, 5.6K 5v to collector

NAND notes: 14:03 (2006.10.05:3 tech_notes#290 xxxxx_at_piksel_notes#46 research#95)

the NAND inputs must normally be logic 1 to avoid affecting the latching action, the inputs are considered to be inverted in this circuit.

it is forbidden to have both inputs at a logic 0 level at the same time. That state will force both outputs to a logic 1, overriding the feedback latching action. In this condition, whichever input goes to logic 1 first will lose control, while the other input (still at logic 0) controls the resulting state of the latch. If both inputs go to logic 1 simultaneously, the result is a "race" condition, and the final state of the latch cannot be determined ahead of time.

http://www.play-hookey.com/digital/rs_nand_latch.html again

links: 11:47 (tech_notes#289)

Pyastra: python assembler translator (for PIC micros):

http://pyastra.sourceforge.net/

reminder for FPGA workflow: 11:40 (2006.10.05:1 fpga#16 tech_notes#288)

To construct components from HDL description in Xilinx WebPAck ISE:

Design utilities -> create schematic symbol