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1010/ap

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Ad-hoc PCB manufacture 20:27 (tech_notes#150)

Thanks to:

http://www.semis.demon.co.uk/PCB/PCB.html

pictures to follow

0) Make board tracks using transfers (from SENO in Germany, bought
   from Conrad) and an Edding 780 black marker

1) Heat up boiling water

2) Mix one 250g pack of Eisen III Cloride granules (Ferric Chloride
   III) again from Conrad in 1 Litre water in a glass jar

3) Pour boiling water into a small bucket

4) Place jar of Eisen solution in the bucket

5) While waiting to heat up drill 1mm holes in boards and tie with
   a metre or so of thread

6) Check every five minutes by pulling out boards. Etching should take
   around 15 minutes.

7) Dunk boards in cold water and rinse a few times

8) Scour boards with washing up pads (damp) to remove black stuff

9) Drill and solder up

working on a design 14:47 (tech_notes#149)

for a neural-network based synthesiser (a la older one with pins and crocodile clips) but totally reconfigurable by way of software - we have say 0-127 7 bits on parallel port which can set two 8x8 grids of connections within circuitry (8 circuits) - the second grid mapping voltages at points within the 8 circuits to the actual switching action of itself (what if can't sink so much current?).

we need to multiplex the parallel port 7 bits to 128 and latch these for the 4016 switches (4 switches in each) = 32 of these

we could imagine using 74LS373 Octal D-type transparent latches for latching (16 of these)

but to multiplex - 4 line to 16 line (74LS154) - two of these in grid connected in some AND gate configuration with latches.

questions:

1) how this could be simplified?

we need 8 latches

we're trying to decode 7 bit data representing one of 128 possible switches

address decoder?

see:

http://www.cgs.synth.net/other/paraport/paraport.html

74LS138 latches (3 to 8)

or even more simply::

http://computerchristmas.com/?link=how_to&:=25

following:

The design is based on 74HC595 shift register chips. The data is sent out serially one bit at a time and shifted through the chips. Each chip has 8 outputs, which drive 8 SSR's or Mosfets etc.

In the case of a 64-port system 64 bits of data are shifted out one at a time for each update. A latching pulse then latches the new data into all chips.

or PIC16F877 plus four 74LS154 plus latches

2) whether we can achieve same functionality in FPGA?

3) whether we should interface to PIC18F and start using purrr?